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IDT7037 PDF预览

IDT7037

更新时间: 2024-10-27 22:57:19
品牌 Logo 应用领域
艾迪悌 - IDT /
页数 文件大小 规格书
17页 151K
描述
HIGH-SPEED 32K x 18 DUAL-PORT STATIC RAM

IDT7037 数据手册

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HIGH-SPEED  
IDT7037L  
32K x 18 DUAL-PORT  
STATIC RAM  
Features  
M/S = VIH for BUSY output flag on Master,  
M/S = VIL for BUSY input on Slave  
Interrupt Flag  
True Dual-Ported memory cells which allow simultaneous  
reads of the same memory location  
High-speed access  
On-chip port arbitration logic  
– Commercial:15/20ns (max.)  
Low-power operation  
Full on-chip hardware support of semaphore signaling  
between ports  
IDT7037L  
Fully asynchronous operation from either port  
Separate upper-byte and lower-byte controls for multi-  
plexed bus and bus matching compatibility  
TTL-compatible, single 5V (±10%) power supply  
Available in a 100-pin TQFP  
Active:1W(typ.)  
Standby: 1mW (typ.)  
Dual chip enables allow for depth expansion without  
external logic  
IDT7037 easily expands data bus width to 36 bits or  
more using the Master/Slave select when cascading more  
than one device  
Industrial temperature range (–40°C to +85°C) is available  
for selected speeds  
FunctionalBlockDiagram  
R/WL  
UBL  
R/WR  
UBR  
CE0L  
CE0R  
CE1L  
CE1R  
OER  
LBR  
OEL  
LBL  
I/O 9-17L  
I/O9-17R  
I/O  
Control  
I/O  
Control  
0-8L  
I/O  
I/O0-8R  
(1,2)  
(1,2)  
BUSYR  
BUSYL  
32Kx18  
14L  
A14R  
A
Address  
Decoder  
Address  
Decoder  
MEMORY  
ARRAY  
7037  
A0L  
A0R  
15  
15  
ARBITRATION  
INTERRUPT  
SEMAPHORE  
LOGIC  
CE0R  
CE0L  
CE1L  
OEL  
CE1R  
OER  
R/WL  
WR  
R/  
SEML  
INTL  
SEMR  
(2)  
(2)  
INTR  
S(1)  
M/  
NOTES:  
4838 drw 01  
1. BUSY is an input as a Slave (M/S = VIL) and an output when it is a Master (M/S = VIH).  
2. BUSY and INT are non-tri-state totem-pole outputs (push-pull).  
JANUARY 2001  
1
DSC-4838/2  
©2000IntegratedDeviceTechnology,Inc.  

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