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IDT7037L15PF9 PDF预览

IDT7037L15PF9

更新时间: 2024-10-28 18:54:27
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器内存集成电路
页数 文件大小 规格书
17页 160K
描述
Dual-Port SRAM, 32KX18, 15ns, CMOS, PQFP100, TQFP-100

IDT7037L15PF9 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:QFP
包装说明:TQFP-100针数:100
Reach Compliance Code:compliantECCN代码:3A991.B.2.B
HTS代码:8542.32.00.41风险等级:5.92
最长访问时间:15 nsJESD-30 代码:S-PQFP-G100
JESD-609代码:e0长度:14 mm
内存密度:589824 bit内存集成电路类型:DUAL-PORT SRAM
内存宽度:18湿度敏感等级:3
功能数量:1端子数量:100
字数:32768 words字数代码:32000
工作模式:ASYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:32KX18
封装主体材料:PLASTIC/EPOXY封装代码:LFQFP
封装形状:SQUARE封装形式:FLATPACK, LOW PROFILE, FINE PITCH
并行/串行:PARALLEL峰值回流温度(摄氏度):240
认证状态:Not Qualified座面最大高度:1.6 mm
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:TIN LEAD端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:20宽度:14 mm
Base Number Matches:1

IDT7037L15PF9 数据手册

 浏览型号IDT7037L15PF9的Datasheet PDF文件第2页浏览型号IDT7037L15PF9的Datasheet PDF文件第3页浏览型号IDT7037L15PF9的Datasheet PDF文件第4页浏览型号IDT7037L15PF9的Datasheet PDF文件第5页浏览型号IDT7037L15PF9的Datasheet PDF文件第6页浏览型号IDT7037L15PF9的Datasheet PDF文件第7页 
HIGH-SPEED  
32K x 18 DUAL-PORT  
STATIC RAM  
IDT7037L  
Features  
M/S = VIH for BUSY output flag on Master,  
M/S = VIL for BUSY input on Slave  
Interrupt Flag  
On-chip port arbitration logic  
Full on-chip hardware support of semaphore signaling  
between ports  
Fully asynchronous operation from either port  
Separate upper-byte and lower-byte controls for multi-  
plexed bus and bus matching compatibility  
TTL-compatible, single 5V (±10%) power supply  
Available in a 100-pin TQFP  
True Dual-Ported memory cells which allow simultaneous  
reads of the same memory location  
High-speed access  
– Commercial:15/20ns (max.)  
Low-power operation  
IDT7037L  
Active:1W(typ.)  
Standby: 1mW (typ.)  
Dual chip enables allow for depth expansion without  
external logic  
IDT7037 easily expands data bus width to 36 bits or  
more using the Master/Slave select when cascading more  
than one device  
Industrial temperature range (–40°C to +85°C) is available  
for selected speeds  
FunctionalBlockDiagram  
R/W  
L
R/WR  
UBL  
UBR  
CE0L  
CE0R  
CE1L  
CE1R  
OE  
R
OE  
L
L
LBR  
LB  
I/O9-17L  
I/O9-17R  
I/O0-8R  
I/O  
Control  
I/O  
Control  
0-8L  
I/O  
(1,2)  
(1,2)  
BUSY  
R
BUSY  
L
32Kx18  
14L  
A
14R  
0R  
A
Address  
Decoder  
Address  
Decoder  
MEMORY  
ARRAY  
7037  
0L  
A
A
15  
15  
ARBITRATION  
INTERRUPT  
SEMAPHORE  
LOGIC  
CE0R  
CE0L  
CE1L  
CE1R  
OEL  
OER  
R/W  
L
R/WR  
SEM  
L
(2)  
SEM  
R
(2)  
INTR  
INT  
L
M/S(1)  
NOTES:  
4838 drw 01  
1. BUSY is an input as a Slave (M/S = VIL) and an output when it is a Master (M/S = VIH).  
2. BUSY and INT are non-tri-state totem-pole outputs (push-pull).  
JANUARY 2001  
1
DSC-4838/2  
©2000IntegratedDeviceTechnology,Inc.  

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