Datasheet > IDT7035S/L

IDT7035S/L

更新时间： 2024-11-28 04:58:19

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
19页	192K
描述
HIGH-SPEED 8K x 18 DUAL-PORT STATIC RAM

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中文翻译

获取价格

数据手册

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IDT7035S/L 数据手册

HIGH-SPEED

IDT7035S/L

8K x 18 DUAL-PORT

STATIC RAM

Features

◆

True Dual-Ported memory cells which allow simultaneous

using the Master/Slave select when cascading more than

one device

M/S = H for BUSY output flag on Master

M/S = L for BUSY input on Slave

Interrupt Flag

On-chip port arbitration logic

reads of the same memory location

High-speed access

◆

Commercial: 15/20ns (max.)

Low-power operation

◆

IDT7035S

Active:800mW(typ.)

Standby: 5mW (typ.)

IDT7035L

Full on-chip hardware support of semaphore signaling

between ports

◆

Fully asynchronous operation from either port

Battery backup operation2V data retention

TTL-compatible, single 5V (±10%) power supply

Available in 100-pin Thin Quad Flatpack

Industrial temperature range (40°C to +85°C) is available

for selected speeds

Active:800mW(typ.)

Standby: 1mW (typ.)

Separate upper-byte and lower-byte control for multiplexed

◆

bus compatibility

IDT7035 easily expands data bus width to 36 bits or more

◆

FunctionalBlockDiagram

R/WL

UBL

R/WR

UBR

LBL

CEL

OEL

LBR

CER

OER

I/O9L-I/O17L

I/O9R-I/O17R

I/O

Control

I/O0L-I/O8L

I/O0R-I/O8R

(1,2)

BUSYL

(1,2)

BUSYR

A12L

A12R

Address

Decoder

MEMORY

ARRAY

Address

Decoder

A0L

A0R

ARBITRATION

INTERRUPT

SEMAPHORE

LOGIC

CEL

OEL

CER

OER

R/WL

R/WR

SEMR

INTR

SEML

INTL

(2)

M/S

4088 drw 01

NOTES:

1. (MASTER): BUSY is output; (SLAVE): BUSY is input.

2. BUSY outputs and INT outputs are non-tri-stated push-pull.

SEPTEMBER 1999

DSC 4088/5

12 3 4 5 6 7...19

中文翻译

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IDT7035S20PFG	IDT	获取价格	Dual-Port SRAM, 8KX8, 20ns, CMOS, PQFP100, 14 X 14 MM, 1.40 MM HEIGHT, TQFP-100
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