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IDT703517S233RM PDF预览

IDT703517S233RM

更新时间: 2024-11-28 18:41:23
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器内存集成电路
页数 文件大小 规格书
20页 874K
描述
QDR SRAM, 256KX36, 0.45ns, PBGA576, 25 X 25 MM, 2.55 MM HEIGHT, 1 MM PITCH, ROHS COMPLIANT, FBGA-576

IDT703517S233RM 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:BGA
包装说明:BGA,针数:576
Reach Compliance Code:compliantECCN代码:3A991.B.2.A
HTS代码:8542.32.00.41风险等级:5.8
最长访问时间:0.45 nsJESD-30 代码:S-PBGA-B576
JESD-609代码:e3长度:25 mm
内存密度:9437184 bit内存集成电路类型:QDR SRAM
内存宽度:36功能数量:1
端子数量:576字数:262144 words
字数代码:256000工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:256KX36封装主体材料:PLASTIC/EPOXY
封装代码:BGA封装形状:SQUARE
封装形式:GRID ARRAY并行/串行:PARALLEL
峰值回流温度(摄氏度):260认证状态:Not Qualified
座面最大高度:2.55 mm最大供电电压 (Vsup):1.9 V
最小供电电压 (Vsup):1.7 V标称供电电压 (Vsup):1.8 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:MATTE TIN
端子形式:BALL端子节距:1 mm
端子位置:BOTTOM处于峰值回流温度下的最长时间:30
宽度:25 mmBase Number Matches:1

IDT703517S233RM 数据手册

 浏览型号IDT703517S233RM的Datasheet PDF文件第2页浏览型号IDT703517S233RM的Datasheet PDF文件第3页浏览型号IDT703517S233RM的Datasheet PDF文件第4页浏览型号IDT703517S233RM的Datasheet PDF文件第5页浏览型号IDT703517S233RM的Datasheet PDF文件第6页浏览型号IDT703517S233RM的Datasheet PDF文件第7页 
PRELIMINARY DATASHET  
IDT70P3537  
512K/256K x36  
SYNCHRONOUS  
DUAL QDR-II  
TM  
IDT70P3517  
®
Features  
each port  
– Four word transfers each of Read & Write per clock cycle per  
port (four word bursts on 2 ports)  
Octal Data Rate  
Port Enable pins (E0,E1) for depth expansion  
Dual Echo Clock Output with DLL-based phase alignment  
High Speed Transceiver Logic inputs  
18Mb Density (512K x 36)  
– Also available 9Mb Density (256K x 36)  
QDR-II x 36 Burst-of-2 Interface  
– Commercial: 233MHz, 250MHz  
Two independent ports  
– True Dual-Port Access to common memory  
Separate, Independent Read and Write Data Buses on each  
Port  
– scaled to receive signals from 1.4V to 1.9V  
Scalable output drivers  
– Drives HSTL, 1.8V TTL or any voltage level from 1.4V to 1.9V  
– Output impedance adjustable from 35 ohms to 70 ohms  
1.8V Core Voltage (VDD)  
576-ball Flip Chip BGA (25mm x 25mm, 1.0mm ball pitch)  
JTAG Interface - IEEE 1149.1 Compliant  
– Supports concurrent transactions  
Two-Word Burst on all DPRAM accesses  
DDR (Double Data Rate) Multiplexed Address Bus  
– One Read and One Write request per clock cycle  
DDR (Double Data Rate) Data Buses  
– Four word burst data (Two Read and Two Write) per clock on  
Functional Block Diagram  
VREFL  
VREFR  
E
P[1:0]  
ER[1:0]  
EL[1:0]  
LEFT PORT  
DATA  
RIGHT PORT  
DATA  
REGISTER  
AND LOGIC  
REGISTER  
AND LOGIC  
D
0L- D35L  
D
0R-  
D35R  
WRITE DRIVER  
KR  
KL  
KL  
KL  
KR  
KR  
(1)  
(1)  
ZQL  
ZQR  
Q
0L-  
Q
3 5L  
Q
0R- Q35 R  
512/256K x 36  
MEMORY  
ARRAY  
CQL, CQL  
CQR, CQR  
K
L
KR  
CR  
CL  
(2)  
A
0R- 17R  
(2)  
A
0L- 17L  
A
A
C
R
, C  
R
C
L
, C  
L
RR  
OR K  
R
, KR  
OR K  
L
, KL  
RL  
LEFT PORT  
ADDRESS  
REGISTER  
AND LOGIC  
RIGHT PORT  
ADDRESS  
REGISTER  
AND LOGIC  
WR  
WL  
ADDRESS DECODE  
BW0R- BW3R  
BW0L- BW3L  
KR  
KL  
KR  
KL  
TCK  
TMS  
TRST  
TDI  
5677 drw01  
JTAG  
VREFR  
VREFL  
TDO  
NOTES:  
1. Input pin to adjust the device outputs to the system data bus impedance.  
2. Address A17 is a INC for IDT70P3517. Disabled input pin (Diode tied to VDD and VSS).  
July 16, 2007  
DSC-5677/1  
©2007 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice. NOT AN OFFER FOR SALE The information  
presented herein is subject to a Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale  
or an offer for sale that creates a contractual power of acceptance. "QDR SRAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress Semicondor, IDT, and Micron Tecnology, Inc."  

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