Datasheet > 存储 > SRAM> IDT7034S20PFI

IDT7034S20PFI

更新时间： 2024-10-28 12:57:59

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
19页	201K
描述
Dual-Port SRAM, 4KX18, 20ns, CMOS, PQFP100, 14 X 14 MM, 1.40 MM HEIGHT, TQFP-100

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中文翻译

获取价格

技术参数
数据手册

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IDT7034S20PFI 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	零件包装代码：	QFP
包装说明：	LFQFP, QFP100,.63SQ,20	针数：	100
Reach Compliance Code：	not_compliant	ECCN代码：	EAR99
HTS代码：	8542.32.00.41	风险等级：	5.31
Base Number Matches：	1

IDT7034S20PFI 数据手册

IDT7034S/L

HIGH-SPEED

4K x 18 DUAL-PORT

STATIC RAM

Features:

◆

using the Master/Slave select when cascading more than

one device

M/S = H for BUSY output flag on Master

M/S = L for BUSY input on Slave

Interrupt Flag

On-chip port arbitration logic

True Dual-Ported memory cells which allow simultaneous

reads of the same memory location

High-speed access

◆

Commercial: 15/20ns (max.)

Low-power operation

◆

IDT7034S

Full on-chip hardware support of semaphore signaling

between ports

Active: 850mW (typ.)

Standby: 5mW (typ.)

IDT7034L

◆

Fully asynchronous operation from either port

Battery backup operation2V data retention

TTL-compatible, single 5V (±10%) power supply

Available in 100-pin Thin Quad Flatpack

Industrial temperature range (40°C to +85°C) is available

for selected speeds

Active: 850mW (typ.)

Standby: 1mW (typ.)

Separate upper-byte and lower-byte control for multiplexed

◆

bus compatibility

IDT7034 easily expands data bus width to 36 bits or more

◆

Functional Block Diagram

R/WL

UBL

R/WR

UBR

LBL

CEL

OEL

LBR

CER

OER

I/O9L-I/O17L

I/O9R-I/O17R

I/O

Control

I/O0L-I/O8L

I/O -I/O

(1,2)

BUSYL

(1,2)

BUSYR

A11L

A11R

A0R

Address

Decoder

MEMORY

ARRAY

Address

Decoder

A0L

ARBITRATION

INTERRUPT

SEMAPHORE

LOGIC

CER

OER

CEL

OEL

R/WL

R/WR

SEMR

(2)

SEML

(2)

INTR

M/S

INTL

4089 drw 01

NOTES:

1. (MASTER): BUSY is output; (SLAVE): BUSY is input.

2. BUSY outputs and INT outputs are non-tri-stated push-pull.

SEPTEMBER 1999

DSC 4089/6

12 3 4 5 6 7...19

中文翻译

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