Datasheet > IDT5V9882T

IDT5V9882T

更新时间： 2024-11-29 11:16:03

品牌	Logo	应用领域
艾迪悌 - IDT		时钟发生器可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数	文件大小	规格书
31页	208K
描述
3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR

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IDT5V9882T 数据手册

IDT5V9882T

INDUSTRIALTEMPERATURERANGE

3.3V EEPROMPROGRAMMABLECLOCKGENERATOR

IDT5V9882T

3.3V EEPROM

PROGRAMMABLE CLOCK

GENERATOR

FEATURES:

DESCRIPTION:

• Three internal PLLs

TheIDT5V9882Tisaprogrammableclockgeneratorintendedforhigh

performancedata-communications,telecommunications,consumer,and

networking applications. There are three internal PLLs, each individually

programmable,allowingforthreeuniquenon-integer-relatedfrequencies.

The frequencies are generated from a single reference clock. The

reference clock can come from one of the two redundant clock inputs. A

glitchless automatic or manual switchover function allows any one of the

redundant clocks to be selected during normal operation.

• Internal non-volatile EEPROM

• FAST mode I²C serial interfaces

• Input Frequency Ranges: 1MHz to 400MHz

• Output Frequency Ranges: 4.9kHz to 500MHz

• Reference Crystal Input with programmable oscillator gain and

programmable linear load capacitance

− Crystal Frequency Range: 8MHz to 50MHz

• Each PLL has an 8-bit pre-scaler and a 12-bit feedback-divider

• 10-bit post-divider blocks

The IDT5V9882T can be programmed through the use of the I²C

interfaces. The programming interface enables the device to be pro-

grammedwhenitisinnormaloperationorwhatiscommonlyknownasin-

systemprogrammable. AninternalEEPROMallowstheusertosaveand

restore the configuration of the device without having to reprogram it on

power-up.

• Fractional Dividers

• Two of the PLLs support Spread Spectrum Generation

capability

• I/O Standards:

− Outputs - 3.3V LVTTL/ LVCMOS, LVPECL, and LVDS

− Inputs - 3.3V LVTTL/ LVCMOS

• Programmable Slew Rate Control

• Programmable Loop Bandwidth Settings

• Programmable output inversion to reduce bimodal jitter

• Individual output enable/disable

• Power-down mode

Each of the three PLLs has an 8-bit pre-scaler and a 12-bit feedback

divider. Thisallowstheusertogeneratethreeuniquenon-integer-related

frequencies. The PLL loop bandwidth is programmable to allow the user

totailorthePLLresponsetotheapplication. Forinstance,theusercantune

the PLL parameters to minimize jitter generation or to maximize jitter

attenuation. Spread spectrum generation and fractional divides are

allowed on two of the PLLs.

• 3.3VVDD

• Available in TSSOP package

Thereare10-bitpostdividersonfiveofthesixoutputbanks. Twoofthe

six output banks are configurable to be LVTTL, LVPECL, or LVDS. The

otherfouroutputbanksareLVTTL. TheoutputsareconnectedtothePLLs

via the switch matrix. The switch matrix allows the user to route the PLL

outputstoanyoutputbank. Thisfeaturecanbeusedtosimplifyandoptimize

the board layout. In addition, each output's slew rate and enable/disable

function can be programmed.

TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.

INDUSTRIAL TEMPERATURE RANGE

JUNE 2010

2010 Integrated Device Technology, Inc.

DSC 7064/2

12 3 4 5 6 7...31

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与IDT5V9882T相关器件

型号	品牌	获取价格	描述	数据表
IDT5V9885	IDT	获取价格	3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR
IDT5V9885B	IDT	获取价格	3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR
IDT5V9885BNLGI	IDT	获取价格	3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR
IDT5V9885BPFGI	IDT	获取价格	3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR
IDT5V9885BPFGI8	IDT	获取价格	Clock Generator, PQFP32
IDT5V9885CNLGI	IDT	获取价格	3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR
IDT5V9885CPFGI	IDT	获取价格	3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR
IDT5V9885NLGI	IDT	获取价格	3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR
IDT5V9885PFGI	IDT	获取价格	3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR
IDT5V9885PFGI8	IDT	获取价格	Clock Generator, 500MHz, PQFP32, GREEN, TQFP-32

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