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IDT5V9910A-7SO PDF预览

IDT5V9910A-7SO

更新时间: 2024-11-26 22:55:27
品牌 Logo 应用领域
艾迪悌 - IDT 时钟驱动器
页数 文件大小 规格书
6页 91K
描述
3.3V LOW SKEW PLL CLOCK DRIVER TURBOCLOCK JR

IDT5V9910A-7SO 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Active零件包装代码:SOIC
包装说明:SOP, SOP24,.4针数:24
Reach Compliance Code:not_compliantHTS代码:8542.39.00.01
风险等级:5.5系列:5V
输入调节:STANDARDJESD-30 代码:R-PDSO-G24
JESD-609代码:e0长度:15.4178 mm
逻辑集成电路类型:PLL BASED CLOCK DRIVER最大I(ol):0.012 A
湿度敏感等级:1功能数量:1
反相输出次数:端子数量:24
实输出次数:8最高工作温度:70 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP24,.4
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):225电源:3.3 V
Prop。Delay @ Nom-Sup:0.7 ns认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.75 ns座面最大高度:2.6416 mm
子类别:Clock Drivers最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):3.3 V
表面贴装:YES温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:7.5057 mm
最小 fmax:85 MHzBase Number Matches:1

IDT5V9910A-7SO 数据手册

 浏览型号IDT5V9910A-7SO的Datasheet PDF文件第2页浏览型号IDT5V9910A-7SO的Datasheet PDF文件第3页浏览型号IDT5V9910A-7SO的Datasheet PDF文件第4页浏览型号IDT5V9910A-7SO的Datasheet PDF文件第5页浏览型号IDT5V9910A-7SO的Datasheet PDF文件第6页 
3.3V LOW SKEW  
IDT5V9910A  
PLL CLOCK DRIVER  
TURBOCLOCK™ JR.  
FEATURES:  
DESCRIPTION:  
The IDT5V9910A is a high fanout phase locked-loop clock driver  
intendedforhighperformancecomputinganddata-communicationsappli-  
cations. Ithas eightzerodelayLVTTLoutputs.  
When the GND/sOE pin is held low, all the outputs are synchronously  
enabled.However,ifGND/sOE is heldhigh,allthe outputs exceptQ2 and  
Q3 are synchronouslydisabled.  
Furthermore, when the VCCQ/PE is held high, all the outputs are  
synchronizedwiththe positive edge ofthe REFclockinput. WhenVCCQ/  
PEis heldlow,allthe outputs are synchronizedwiththe negative edge of  
REF.  
TheFBsignaliscomparedwiththeinputREFsignalatthephasedetector  
inordertodrive the VCO.Phase differences cause the VCOofthe PLLto  
adjust upwards or downwards accordingly.  
Aninternalloopfiltermoderates the response ofthe VCOtothe phase  
detector.Theloopfiltertransferfunctionhasbeenchosentoprovideminimal  
jitter(orfrequencyvariation)whilestillprovidingaccurateresponsestoinput  
frequencychanges.  
• Eight zero delay outputs  
• <250ps of output to output skew  
• Selectable positive or negative edge synchronization  
• Synchronous output enable  
• Output frequency: 15MHz to 85MHz  
• 3 skew grades:  
IDT5V9910A-2: tSKEW0<250ps  
IDT5V9910A-5: tSKEW0<500ps  
IDT5V9910A-7: tSKEW0<750ps  
• 3-level inputs for PLL range control  
• PLL bypass for DC testing  
• External feedback, internal loop filter  
• 12mA balanced drive outputs  
Low Jitter: <200ps peak-to-peak  
Available in SOIC package  
FUNCTIONALBLOCKDIAGRAM  
VCCQ/PE  
GND/sOE  
Q0  
Q1  
Q2  
Q3  
Q4  
Q5  
Q6  
Q7  
FB  
PLL  
REF  
FS  
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.  
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES  
SEPTEMBER 2001  
1
c
2001 Integrated Device Technology, Inc.  
DSC 5847/1  

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