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IDT5V991A-2J PDF预览

IDT5V991A-2J

更新时间: 2024-11-26 21:54:15
品牌 Logo 应用领域
艾迪悌 - IDT 时钟驱动器逻辑集成电路
页数 文件大小 规格书
8页 79K
描述
3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK

IDT5V991A-2J 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:QFJ
包装说明:QCCJ, LDCC32,.5X.6针数:32
Reach Compliance Code:not_compliantHTS代码:8542.39.00.01
风险等级:5.84Is Samacsys:N
系列:5V输入调节:STANDARD
JESD-30 代码:R-PQCC-J32JESD-609代码:e0
长度:13.97 mm逻辑集成电路类型:PLL BASED CLOCK DRIVER
最大I(ol):0.012 A湿度敏感等级:1
功能数量:1反相输出次数:
端子数量:32实输出次数:8
最高工作温度:70 °C最低工作温度:
封装主体材料:PLASTIC/EPOXY封装代码:QCCJ
封装等效代码:LDCC32,.5X.6封装形状:RECTANGULAR
封装形式:CHIP CARRIER峰值回流温度(摄氏度):225
电源:3.3 V认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.5 ns座面最大高度:3.429 mm
子类别:Clock Drivers最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):3.3 V
表面贴装:YES温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn85Pb15)端子形式:J BEND
端子节距:1.27 mm端子位置:QUAD
处于峰值回流温度下的最长时间:20宽度:11.43 mm
最小 fmax:85 MHzBase Number Matches:1

IDT5V991A-2J 数据手册

 浏览型号IDT5V991A-2J的Datasheet PDF文件第2页浏览型号IDT5V991A-2J的Datasheet PDF文件第3页浏览型号IDT5V991A-2J的Datasheet PDF文件第4页浏览型号IDT5V991A-2J的Datasheet PDF文件第5页浏览型号IDT5V991A-2J的Datasheet PDF文件第6页浏览型号IDT5V991A-2J的Datasheet PDF文件第7页 
IDT5V991A  
3.3V PROGRAMMABLE  
SKEW PLL CLOCK DRIVER  
TURBOCLOCK™  
FEATURES:  
DESCRIPTION:  
• REF is 5V tolerant  
The IDT5V991Ais a highfanout3.3VPLLbasedclockdriverintended  
forhighperformancecomputinganddata-communicationsapplications.A  
keyfeatureoftheprogrammableskewistheabilityofoutputstoleadorlag  
the REF input signal. The IDT5V991A has eight programmable skew  
outputs infourbanks of2.Skewis controlledby3-levelinputsignals that  
may be hard-wired to appropriate HIGH-MID-LOW levels.  
• 4 pairs of programmable skew outputs  
Low skew: 200ps same pair, 250ps all outputs  
• Selectable positive or negative edge synchronization:  
Excellent for DSP applications  
• Synchronous output enable  
• Output frequency: 3.75MHz to 85MHz  
• 2x, 4x, 1/2, and 1/4 outputs  
Whenthe GND/sOE pinis heldlow,allthe outputs are synchronously  
enabled.However,ifGND/sOEisheldhigh,alltheoutputsexcept3Q0and  
3Q1 are synchronously disabled.  
• 3 skew grades:  
IDT5V991A-2: tSKEW0<250ps  
IDT5V991A-5: tSKEW0<500ps  
IDT5V991A-7: tSKEW0<750ps  
• 3-level inputs for skew and PLL range control  
• PLL bypass for DC testing  
Furthermore, when the VCCQ/PE is held high, all the outputs are  
synchronizedwiththe positive edge ofthe REFclockinput.WhenVCCQ/  
PEis heldlow,allthe outputs are synchronizedwiththe negative edge of  
REF. BothdeviceshaveLVTTLoutputswith12mAbalanceddriveoutputs.  
• External feedback, internal loop filter  
• 12mA balanced drive outputs  
Low Jitter: <200ps peak-to-peak  
Available in 32-pin PLCC Package  
FUNCTIONALBLOCKDIAGRAM  
GND/sOE  
1Q0  
Skew  
Select  
1Q1  
3
3
1F1:0  
2F1:0  
3F1:0  
4F1:0  
VCCQ/PE  
2Q0  
2Q1  
Skew  
Select  
3
3
3
3
REF  
PLL  
FB  
3Q0  
3Q1  
Skew  
Select  
3
3
FS  
4Q0  
4Q1  
Skew  
Select  
3
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.  
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES  
SEPTEMBER 2001  
1
c
2001 Integrated Device Technology, Inc.  
DSC 5963/3  

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