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IDT5V9910A-2SOC PDF预览

IDT5V9910A-2SOC

更新时间: 2024-11-28 23:57:55
品牌 Logo 应用领域
其他 - ETC 时钟驱动器输出元件
页数 文件大小 规格书
6页 98K
描述
EIGHT DISTRIBUTED-OUTPUT CLOCK DRIVER|SOP|24PIN|PLASTIC

IDT5V9910A-2SOC 数据手册

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3.3V LOW SKEW  
IDT5V9910A  
PLL CLOCK DRIVER  
TURBOCLOCK™ JR.  
FEATURES:  
DESCRIPTION  
EightzerodelayLVTTLoutputs  
<250ps ofoutputtooutputskew  
Selectable positive ornegative edge synchronization  
Synchronous outputenable  
Outputfrequency:15MHzto85MHz  
3 skew grades:  
IDT5V9910A-2:tSKEW0<250ps  
IDT5V9910A-5:tSKEW0<500ps  
IDT5V9910A-7:tSKEW0<750ps  
3-level input for PLL range control  
PLL bypass for DC testing  
Externalfeedback,internalloopfilter  
12mAbalanceddrive outputs  
LowJitter:<200ps peak-to-peak  
Available inSOICPackage  
The IDT5V9910A is a high fanout phase locked-loop clock driver  
intendedforhighperformancecomputinganddata-communicationsappli-  
cations. Ithas eightzerodelayLVTTLoutputs.  
When the GND/sOE pin is held low, all the outputs are synchronously  
enabled.However,ifGND/sOEis heldhigh,allthe outputs exceptQ2 and  
Q3 are synchronouslydisabled.  
Furthermore, when the VCCQ/PE is held high, all the outputs are  
synchronizedwiththe positive edge ofthe REFclockinput. WhenVCCQ/  
PEis heldlow,allthe outputs are synchronizedwiththe negative edge of  
REF.  
TheFBsignaliscomparedwiththeinputREFsignalatthephasedetector  
inordertodrive the VCO.Phase differences cause the VCOofthe PLLto  
adjust upwards or downwards accordingly.  
Aninternalloopfiltermoderates the response ofthe VCOtothe phase  
detector.Theloopfiltertransferfunctionhasbeenchosentoprovideminimal  
jitter(orfrequencyvariation)whilestillprovidingaccurateresponsestoinput  
frequencychanges.  
FUNCTIONALBLOCKDIAGRAM  
VCCQ/PE  
GND/sOE  
Q0  
Q1  
Q2  
Q3  
Q4  
Q5  
Q6  
Q7  
FB  
PLL  
REF  
FS  
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES  
AUGUST 2000  
1
c
2000 Integrated Device Technology, Inc.  
DSC - 5847  

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