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IDT5V9888NLGI8 PDF预览

IDT5V9888NLGI8

更新时间: 2024-11-30 06:52:47
品牌 Logo 应用领域
艾迪悌 - IDT /
页数 文件大小 规格书
37页 340K
描述
Clock Generator, 500MHz, PQCC28, GREEN, PLASTIC, VFQFPN-28

IDT5V9888NLGI8 数据手册

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IDT5V9888  
3.3V EEPROM  
PROGRAMMABLE CLOCK  
GENERATOR  
FEATURES:  
DESCRIPTION:  
• Three internal PLLs  
The IDT5V9888 is a programmable clock generator intended for high  
performancedata-communications,telecommunications,consumer,and  
networking applications. There are three internal PLLs, each individually  
programmable,allowingforthreeuniquenon-integer-relatedfrequencies.  
The frequencies are generated from a single reference clock. The  
reference clock can come from one of the two redundant clock inputs. A  
glitchless automatic or manual switchover function allows any one of the  
redundant clocks to be selected during normal operation.  
• Internal non-volatile EEPROM  
• JTAG and FAST mode I2C serial interfaces  
• Input Frequency Ranges: 1MHz to 400MHz  
• Output Frequency Ranges:  
LVTTL: up to 200MHz  
LVPECL/ LVDS: up to 500MHz  
• Reference Crystal Input with programmable oscillator gain and  
programmable linear load capacitance  
Crystal Frequency Range: 8MHz to 50MHz  
• Each PLL has an 8-bit pre-scaler and a 12-bit feedback-divider  
• 10-bit post-divider blocks  
• Fractional Dividers  
• Two of the PLLs support Spread Spectrum Generation  
capability  
• I/O Standards:  
Outputs - 3.3V LVTTL/ LVCMOS, LVPECL, and LVDS  
Inputs - 3.3V LVTTL/ LVCMOS  
• Programmable Slew Rate Control  
• Programmable Loop Bandwidth Settings  
• Programmable output inversion to reduce bimodal jitter  
• Redundant clock inputs with glitchless auto and manual  
switchover options  
TheIDT5V9888canbeprogrammedthroughtheuseoftheI2CorJTAG  
interfaces. The programming interface enables the device to be pro-  
grammedwhenitisinnormaloperationorwhatiscommonlyknownasin-  
systemprogrammable. AninternalEEPROMallowstheusertosaveand  
restore the configuration of the device without having to reprogram it on  
power-up. JTAG boundary scan is also implemented.  
Each of the three PLLs has an 8-bit pre-scaler and a 12-bit feedback  
divider. Thisallowstheusertogeneratethreeuniquenon-integer-related  
frequencies. The PLL loop bandwidth is programmable to allow the user  
totailorthePLLresponsetotheapplication. Forinstance,theusercantune  
the PLL parameters to minimize jitter generation or to maximize jitter  
attenuation. Spread spectrum generation and fractional divides are  
allowed on two of the PLLs.  
Thereare10-bitpostdividersonfiveofthesixoutputbanks. Twoofthe  
six output banks are configurable to be LVTTL, LVPECL, or LVDS. The  
otherfouroutputbanksareLVTTL. TheoutputsareconnectedtothePLLs  
via the switch matrix. The switch matrix allows the user to route the PLL  
outputstoanyoutputbank. Thisfeaturecanbeusedtosimplifyandoptimize  
the board layout. In addition, each output's slew rate and enable/disable  
function can be programmed.  
• JTAG Boundary Scan  
• Individual output enable/disable  
• Power-down mode  
• 3.3VVDD  
• Available in TQFP and VFQFPN packages  
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.  
INDUSTRIAL TEMPERATURE RANGE  
OCTOBER 2007  
1
c
2007 Integrated Device Technology, Inc.  
DSC 7044/13  

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