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ICSSSTUA32866BHT PDF预览

ICSSSTUA32866BHT

更新时间: 2024-11-18 04:30:31
品牌 Logo 应用领域
艾迪悌 - IDT /
页数 文件大小 规格书
27页 307K
描述
D Flip-Flop, SSTU Series, 1-Func, Positive Edge Triggered, 25-Bit, True Output, PBGA96, 5.50 X 13.50 MM, MO-205, LFBGA-96

ICSSSTUA32866BHT 数据手册

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ICSSSTUA32866B  
Integrated  
Circuit  
Systems,Inc.  
25-Bit Configurable Registered Buffer for DDR2  
Pin Configuration  
Recommended Application:  
DDR2 Memory Modules  
1
2
3
4
5
6
Provides complete DDR DIMM solution with  
ICS97ULP877  
Ideal for DDR2 400,533 and 667  
A
B
C
D
E
F
Product Features:  
25-bit 1:1 or 14-bit 1:2 configurable registered buffer  
with parity check functionality  
Supports SSTL_18 JEDEC specification on data  
inputs and outputs  
Supports LVCMOS switching levels on CSR# and  
RESET# inputs  
Low voltage operation  
VDD = 1.7V to 1.9V  
Available in 96 BGA package  
Drop-in replacement for ICSSSTUA32864  
Green packages available  
G
H
J
K
L
M
N
P
R
T
FunctionalityTruthTable  
96 Ball BGA  
(Top View)  
Inputs  
Outputs  
QCS#  
Dn,  
DODT,  
DCKE  
QODT,  
QCKE  
RST#  
DCS#  
CSR#  
CK  
CK#  
Qn  
H
H
H
H
H
H
H
H
H
H
H
H
L
H
X
L
L
L
L
L
L
L
L
L
L
H
H
Q
0
Q
0
Q
0
L or H  
L or H  
L or H  
L or H  
L or H  
L or H  
L
L
L
L
L
L
H
H
H
L
L
H
X
H
H
Q
0
Q
0
Q
0
L
L
L
H
H
H
L
L
L
H
H
H
X
H
H
Q
0
Q
0
Q
0
Q
0
H
H
L
L
H
H
H
H
Q
0
H
X
H
Q
0
Q
0
Q
0
H
H
L or H  
X or  
L or H  
X or  
X or  
X or  
X or  
L
L
L
L
Floating Floating Floating Floating Floating  
1054A—01/28/05  

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