Datasheet > ICSSSTUAF32869AHLFT

ICSSSTUAF32869AHLFT

更新时间： 2024-09-25 19:48:47

品牌	Logo	应用领域
艾迪悌 - IDT		逻辑集成电路触发器
页数	文件大小	规格书
21页	498K
描述
D Flip-Flop, 32869 Series, 1-Func, Positive Edge Triggered, 14-Bit, True Output, PBGA150, LEAD FREE, BGA-150

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ICSSSTUAF32869AHLFT 技术参数

是否Rohs认证：	符合	生命周期：	Obsolete
零件包装代码：	BGA	包装说明：	LEAD FREE, BGA-150
针数：	150	Reach Compliance Code：	compliant
HTS代码：	8542.39.00.01	风险等级：	5.84
系列：	32869	JESD-30 代码：	R-PBGA-B150
JESD-609代码：	e1	长度：	13 mm
逻辑集成电路类型：	D FLIP-FLOP	位数：	14
功能数量：	1	端子数量：	150
最高工作温度：	70 °C	最低工作温度：
输出特性：	OPEN-DRAIN	输出极性：	TRUE
封装主体材料：	PLASTIC/EPOXY	封装代码：	TFBGA
封装形状：	RECTANGULAR	封装形式：	GRID ARRAY, THIN PROFILE, FINE PITCH
峰值回流温度（摄氏度）：	260	传播延迟（tpd）：	1.9 ns
认证状态：	Not Qualified	座面最大高度：	1.2 mm
最大供电电压 (Vsup)：	1.9 V	最小供电电压 (Vsup)：	1.7 V
标称供电电压 (Vsup)：	1.8 V	表面贴装：	YES
温度等级：	COMMERCIAL	端子面层：	TIN SILVER COPPER
端子形式：	BALL	端子节距：	0.65 mm
端子位置：	BOTTOM	处于峰值回流温度下的最长时间：	40
触发器类型：	POSITIVE EDGE	宽度：	8 mm
最小 fmax：	340 MHz	Base Number Matches：	1

ICSSSTUAF32869AHLFT 数据手册

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DATASHEET

14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2

ICSSSTUAF32869A

The ICSSSTUAF32869A includes a parity checking

function. The ICSSSTUAF32869A accepts a parity bit from

the memory controller at its input pin PARIN one or two

cycles after the corresponding data input, compares it with

the data received on the D-inputs and indicates on its

opendrain PTYERR pin (active low) whether a parity error

has occurred. The number of cycles depends on the setting

of C1.

Description

The ICSSSTUAF32869A is 14-bit 1:2 registered buffer with

parity, designed for 1.7 V to 1.9 V VDD operation.

All clock and data inputs are compatible with the JEDEC

standard for SSTL_18. The control inputs are LVCMOS. All

outputs are 1.8V CMOS drivers optimized to drive the

DDR2 DIMM load. They provide 50% more dynamic driver

strength than the standard SSTU32864 outputs.

When used as a single device, the C1 input is tied low.

When used in pairs, the C1 inputs is tied low for the first

PTYERR signals are produced two clock cycles after the

corresponding data input. When used in pairs, the PTYERR

signals of the first register are left floating. The PPO outputs

of the first register are cascaded to the PARIN signas on the

second register (back). The PPO and PTYERR signals of

the second register are produced three clock cycles after

the corresponding data input. Parity implimentation and

device wiring for single and dual die is described in the

diagram below.

The ICSSSTUAF32869A operates from a differential clock

(CLK and CLK). Data are registered at the crossing of CLK

going high, and CLK going low.

The device supports low-power standby operation. When

the reset input (RESET) is low, the differential input

receivers are disabled, and undriven (floating) data, clock

and reference voltage (VREF) inputs are allowed. In

addition, when RESET is low all registers are reset, and all

outputs except PTYERR are forced low. The LVCMOS

RESET input must always be held at a valid logic high or

low level.

To ensure defined outputs from the register before a stable

clock has been supplied, RESET must be held in the low

state during power up.

If an error occurs, and the PTYERR is driven low, it stays

low for two clock cycles or until RESET is driven low. The

DIMM-dependent signals (DCKE, DCS, CSR and DODT)

are not included in the parity check computations.

In the DDR2 RDIMM application, RESET is specified to be

completely asynchronous with respect to CLK and CLK.

Therefore, no timing relationship can be guaranteed

between the two. When entering reset, the register will be

cleared and the outputs will be driven low quickly, relative to

the time to disable the differential input receivers. However,

when coming out of reset, the register will become active

quickly, relative to the time to enable the differential input

receivers. ICSSSTUAF32869A must ensure that the

outputs remain low as long as the data inputs are low, the

clock is stable during the time from the low-to-high

transition of RESET and the input receivers are fully

enabled. This will ensures that there are no glitches on the

output.

All registers used on an individual DIMM must be of the

same configuration, i.e single or dual die.

Features

• 14-bit 1:2 registered buffer with parity check functionality

• Supports SSTL_18 JEDEC specification on data inputs

and outputs

• 50% more dynamic driver strength than standard

SSTU32864

• Supports LVCMOS switching levels on C1 and RESET

inputs

• Low voltage operation: VDD = 1.7V to 1.9V

• Available in 150 BGA package

The device monitors both DCS and CSR inputs and will

gate the Qn, PPO (Paritial-Parity-Out) and PTYERR (Parity

Error) Parity outputs from changing states when both DCS

and CSR are high. If either DCS and CSR input is low, the

Qn, PPO and PTYERR outputs will function normally. The

RESET input has priority over the DCS and CSR controls

and will force the Qn and PPO outputs low and the

PTYERR high.

Applications

• DDR2 Memory Modules

• Provides complete DDR DIMM solution with

ICS98ULPA877A or IDTCSPUA877A

• Ideal for DDR2 400, 533, and 667

14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2

ICSSSTUAF32869A

7095/13

12 3 4 5 6 7...21

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与ICSSSTUAF32869AHLFT相关器件

型号	品牌	获取价格	描述	数据表
ICSSSTUAH32865A	IDT	获取价格	25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
ICSSSTUAH32865AHLFT	IDT	获取价格	25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
ICSSSTUAH32868A	IDT	获取价格	28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
ICSSSTUAH32868AHLF	IDT	获取价格	28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
ICSSSTUAH32868AHLFT	IDT	获取价格	D Flip-Flop, 32868 Series, 1-Func, Positive Edge Triggered, 28-Bit, True Output, PBGA176,
ICSSSTUB32864A	IDT	获取价格	25-Bit Configurable Registered Buffer for DDR2
ICSSSTUB32864AHLF	IDT	获取价格	Interface Circuit
ICSSSTUB32864AHLFT	IDT	获取价格	暂无描述
ICSSSTUB32864AHM	IDT	获取价格	Interface Circuit
ICSSSTUB32864AHMLF	IDT	获取价格	Interface Circuit

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