Datasheet > ICSSSTUAH32865A

ICSSSTUAH32865A

更新时间： 2024-11-13 03:24:39

品牌	Logo	应用领域
艾迪悌 - IDT		双倍数据速率
页数	文件大小	规格书
17页	420K
描述
25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2

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ICSSSTUAH32865A 数据手册

DATASHEET

28-BIT 1:2 REGISTERED BUFFER FOR DDR2

IDT74SSTUBH32865A

The IDT74SSTUBH32865A includes a parity checking

function. The IDT74SSTUBH32865A accepts a parity bit

from the memory controller at its input pin PARIN,

compares it with the data received on the D-inputs and

indicates whether a parity error has occurred on its

open-drain PTYERR pin (active LOW).

Description

This 28-bit 1:2 registered buffer with parity is designed for

1.7V to 1.9V VDD operation.

All clock and data inputs are compatible with the JEDEC

standard for SSTL_18. The control inputs are LVCMOS. All

outputs are 1.8 V CMOS drivers that have been optimized

to drive the DDR2 DIMM load. The IDT74SSTUBH32865A

operates from a differential clock (CLK and CLK). Data are

registered at the crossing of CLK going high, and CLK

going low.

Features

• Double Drive strength for heavily-loaded DIMM

applications

The device supports low-power standby operation. When

the reset input (RESET) is low, the differential input

receivers are disabled, and undriven (floating) data, clock

and reference voltage (VREF) inputs are allowed. In

addition, when RESET is low all registers are reset, and all

outputs except PTYERR are forced low. The LVCMOS

RESET input must always be held at a valid logic high or

low level.

• 28-bit 1:2 registered buffer with parity check functionality

• Supports SSTL_18 JEDEC specification on data inputs

and outputs

• Supports LVCMOS switching levels on CSGateEN and

RESET inputs

• Low voltage operation: VDD = 1.7V to 1.9V

• Available in 160-ball LFBGA package

To ensure defined outputs from the register before a stable

clock has been supplied, RESET must be held in the low

state during power up.

Applications

In the DDR2 RDIMM application, RESET is specified to be

completely asynchronous with respect to CLK and CLK.

Therefore, no timing relationship can be guaranteed

between the two. When entering reset, the register will be

cleared and the outputs will be driven low quickly, relative to

the time to disable the differential input receivers. However,

when coming out of reset, the register will become active

quickly, relative to the time to enable the differential input

receivers. As long as the data inputs are low, and the clock

is stable during the time from the low-to-high transition of

RESET until the input receivers are fully enabled, the

design of the IDT74SSTUBH32865A must ensure that the

outputs will remain low, thus ensuring no glitches on the

output.

• DDR2 Memory Modules

• Provides complete DDR DIMM solution with

ICS98ULPA877A or IDTCSPUA877A

• Ideal for DDR2 400, 533, 667, and 800

The device monitors both DCS0 and DCS1 inputs and will

gate the Qn outputs from changing states when both DCS0

and DCS1 are high. If either DCS0 and DCS1 input is low,

the Qn outputs will function normally. The RESET input has

priority over the DCS0 and DCS1 control and will force the

Qn outputs low and the PTYERR output high. If the

DCS-control functionality is not desired, then the

CSGateEnable input can be hardwired to ground, in which

case, the setup-time requirement for DCS would be the

same as for the other D data inputs.

28-BIT 1:2 REGISTERED BUFFER FOR DDR2

IDT74SSTUBH32865A

7103/10

12 3 4 5 6 7...17

中文翻译

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与ICSSSTUAH32865A相关器件

型号	品牌	获取价格	描述	数据表
ICSSSTUAH32865AHLFT	IDT	获取价格	25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
ICSSSTUAH32868A	IDT	获取价格	28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
ICSSSTUAH32868AHLF	IDT	获取价格	28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
ICSSSTUAH32868AHLFT	IDT	获取价格	D Flip-Flop, 32868 Series, 1-Func, Positive Edge Triggered, 28-Bit, True Output, PBGA176,
ICSSSTUB32864A	IDT	获取价格	25-Bit Configurable Registered Buffer for DDR2
ICSSSTUB32864AHLF	IDT	获取价格	Interface Circuit
ICSSSTUB32864AHLFT	IDT	获取价格	暂无描述
ICSSSTUB32864AHM	IDT	获取价格	Interface Circuit
ICSSSTUB32864AHMLF	IDT	获取价格	Interface Circuit
ICSSSTUB32864AHMLFT	IDT	获取价格	Interface Circuit

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