Datasheet > ICSS98UAE877AHLFT

ICSS98UAE877AHLFT

更新时间： 2024-11-13 21:03:51

品牌	Logo	应用领域
艾迪悌 - IDT		驱动逻辑集成电路
页数	文件大小	规格书
18页	331K
描述
PLL Based Clock Driver, 98UAE Series, 10 True Output(s), 0 Inverted Output(s), PBGA52, LEAD FREE, MO-205/MO-255, VFBGA-52

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ICSS98UAE877AHLFT 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Obsolete	零件包装代码：	BGA
包装说明：	VFBGA-52	针数：	52
Reach Compliance Code：	compliant	HTS代码：	8542.39.00.01
风险等级：	5.77	系列：	98UAE
输入调节：	DIFFERENTIAL	JESD-30 代码：	R-PBGA-B52
JESD-609代码：	e3	长度：	7 mm
逻辑集成电路类型：	PLL BASED CLOCK DRIVER	功能数量：	1
反相输出次数：		端子数量：	52
实输出次数：	10	最高工作温度：	70 °C
最低工作温度：		输出特性：	3-STATE
封装主体材料：	PLASTIC/EPOXY	封装代码：	LFBGA
封装形状：	RECTANGULAR	封装形式：	GRID ARRAY, LOW PROFILE, FINE PITCH
峰值回流温度（摄氏度）：	260	认证状态：	Not Qualified
Same Edge Skew-Max（tskwd）：	0.06 ns	座面最大高度：	1.31 mm
最大供电电压 (Vsup)：	1.575 V	最小供电电压 (Vsup)：	1.425 V
标称供电电压 (Vsup)：	1.5 V	表面贴装：	YES
温度等级：	COMMERCIAL	端子面层：	MATTE TIN
端子形式：	BALL	端子节距：	0.65 mm
端子位置：	BOTTOM	处于峰值回流温度下的最长时间：	30
宽度：	4.5 mm	最小 fmax：	410 MHz
Base Number Matches：	1

ICSS98UAE877AHLFT 数据手册

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DATASHEET

1.5V LOW-POWER WIDE-RANGE FREQUENCY CLOCK DRIVER

ICS98UAE877A

Description

Features

The PLL clock buffer, ICS98UAE877A, is designed for a

VDDQ of 1.5V, an AVDD of 1.5V and differential data input

and output levels.

• Low skew, low jitter PLL clock driver

• 1 to 10 differential clock distribution

• Feedback pins for input to output synchronization

• Spread Spectrum tolerant inputs

• Auto PD when input signal is at a certain logic state

• Available in 52-ball VFBGA and a 40-pin MLF

ICS98UAE877A is a zero delay buffer that distributes a

differential clock input pair (CLK_INT, CLK_INC) to ten

differential pair of clock outputs (CLKT[0:9], CLKC[0:9]) and

one differential pair feedback clock outputs (FB_OUTT,

FBOUTC). The clock outputs are controlled by the input

clocks (CLK_INT, CLK_INC), the feedback clocks (FB_INT,

FB_INC), the LVCMOS program pins (OE, OS) and the

Analog Power input (AVDD). When OE is low, the outputs

(except FB_OUTT/FB_OUTC) are disabled while the

internal PLL continues to maintain its locked-in frequency.

OS (Output Select) is a program pin that must be tied to

GND or VDDQ. When OS is high, OE will function as

described above. When OS is low, OE has no effect on

CLKT7/CLKC7 (they are free running in addition to

FB_OUTT/FB_OUTC). When AVDD is grounded, the PLL is

turned off and bypassed for test purposes.

Applications

• DDR2 Memory Modules / Zero Delay Board Fan Out

• Provides complete DDR DIMM solution with

IDT74SSTUAE32xxx family

Switching Characteristics

• Period jitter:

40ps (DDR2-400/533)

30ps (DDR2-667)

When both clock signals (CLK_INT, CLK_INC) are logic

low, the device will enter a low power mode. An input logic

detection circuit on the differential inputs, independent from

the input buffers, will detect the logic low level and perform

a low power state where all outputs, the feedback and the

PLL are OFF. When the inputs transition from both being

logic low to being differential signals, the PLL will be turned

back on, the inputs and outputs will be enabled and the PLL

• Half-period jitter:

60ps (DDR2-400/533)

50ps (DDR2-667)

• Output-Output Skew 40ps (DDR2-400/533)

30ps (DDR2-667)

• Cycle-Cycle Jitter

40ps

will obtain phase lock between the feedback clock pair

(FB_INT, FB_INC) and the input clock pair (CLK_INT,

CLK_INC) within the specified stabilization time tSTAB.

The PLL in ICS98UAE877A clock driver uses the input

clocks (CLK_INT, CLK_INC) and the feedback clocks

(FB_INT, FB_INC) to provide high-performance, low-skew,

low-jitter output differential clocks (CLKT[0:9], CLKC[0:9]).

ICS98UAE877A is also able to track Spread Spectrum

Clocking (SSC) for reduced EMI.

ICS98UAE877A is available in Commercial Temperature

Range (0°C to 70°C) and Industrial Temperature Range

(-40°C to +85°C). See Ordering Information for details

1.5V LOW-POWER WIDE-RANGE FREQUENCY CLOCK DRIVER

ICS98UAE877A

7181/2

12 3 4 5 6 7...18

中文翻译

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与ICSS98UAE877AHLFT相关器件

型号	品牌	获取价格	描述	数据表
ICSS98UAE877AKLFIT	IDT	获取价格	PLL Based Clock Driver, 98UAE Series, 10 True Output(s), 0 Inverted Output(s), PQCC40, 6 X
ICSS98UAE877AKLFT	IDT	获取价格	PLL Based Clock Driver, 98UAE Series, 10 True Output(s), 0 Inverted Output(s), PQCC40, 6 X
ICSSSTU32864	ICSI	获取价格	25-Bit Configurable Registered Buffer
ICSSSTU32864HT	IDT	获取价格	Interface Circuit
ICSSSTU32866YHLFT	IDT	获取价格	D Flip-Flop, SSTU Series, 1-Func, Positive Edge Triggered, 25-Bit, True Output, PBGA96, BG
ICSSSTU32866YHT	IDT	获取价格	D Flip-Flop, SSTU Series, 1-Func, Positive Edge Triggered, 25-Bit, True Output, PBGA96
ICSSSTUA32864BHLFT	IDT	获取价格	D Flip-Flop, SSTU Series, 1-Func, Positive Edge Triggered, 25-Bit, True Output, PBGA96, 5.
ICSSSTUA32864BHMLFT	IDT	获取价格	D Flip-Flop, SSTU Series, 1-Func, Positive Edge Triggered, 25-Bit, True Output, PBGA96, 5
ICSSSTUA32866BHLFT	IDT	获取价格	D Flip-Flop, SSTU Series, 1-Func, Positive Edge Triggered, 25-Bit, True Output, PBGA96, 5.
ICSSSTUA32866BHMLFT	IDT	获取价格	D Flip-Flop, SSTU Series, 1-Func, Positive Edge Triggered, 25-Bit, True Output, PBGA96, 11

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