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ICS87931BYILF PDF预览

ICS87931BYILF

更新时间: 2024-11-17 21:14:11
品牌 Logo 应用领域
艾迪悌 - IDT 驱动逻辑集成电路
页数 文件大小 规格书
16页 165K
描述
PLL Based Clock Driver, 6 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, MS-026, LQFP-32

ICS87931BYILF 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:QFP
包装说明:7 X 7 MM, 1.40 MM HEIGHT, MS-026, LQFP-32针数:32
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:8.52输入调节:DIFFERENTIAL
JESD-30 代码:S-PQFP-G32JESD-609代码:e3
长度:7 mm逻辑集成电路类型:PLL BASED CLOCK DRIVER
功能数量:1反相输出次数:
端子数量:32实输出次数:6
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:LQFP封装形状:SQUARE
封装形式:FLATPACK, LOW PROFILE峰值回流温度(摄氏度):260
认证状态:Not QualifiedSame Edge Skew-Max(tskwd):0.4 ns
座面最大高度:1.6 mm最大供电电压 (Vsup):3.465 V
最小供电电压 (Vsup):3.135 V标称供电电压 (Vsup):3.3 V
表面贴装:YES温度等级:INDUSTRIAL
端子面层:MATTE TIN端子形式:GULL WING
端子节距:0.8 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:7 mm
Base Number Matches:1

ICS87931BYILF 数据手册

 浏览型号ICS87931BYILF的Datasheet PDF文件第2页浏览型号ICS87931BYILF的Datasheet PDF文件第3页浏览型号ICS87931BYILF的Datasheet PDF文件第4页浏览型号ICS87931BYILF的Datasheet PDF文件第5页浏览型号ICS87931BYILF的Datasheet PDF文件第6页浏览型号ICS87931BYILF的Datasheet PDF文件第7页 
Low Skew, 1-to-6, LVCMOS/LVTTL Clock  
Multiplier/Zero Delay Buffer  
ICS87931I  
GENERAL DESCRIPTION  
FEATURES  
Fully integrated PLL  
The ICS87931I is a low voltage, low skew LVCMOS/LVTTL Clock  
Multiplier/Zero Delay Buffer.With output frequencies up to 150MHz,  
the ICS87931I is targeted for high performance clock applica-  
tions. Along with a fully integrated PLL, the ICS87931I contains  
frequency configurable outputs and an external feedback input  
for regenerating clocks with “zero delay”.  
Six LVCMOS/LVTTL outputs, 7Ω typical output impedance  
Selectable differential CLK0, nCLK0 or LVCMOS/LVTTL  
clock for redundant clock applications  
Maximum output frequency: 150MHz  
VCO range: 220MHz to 480MHz  
Selectable clock inputs, CLK1 and differential CLK0, nCLK0 sup-  
port redundant clock applications.The CLK_SEL input determines  
which reference clock is used. The output divider values of Bank  
A, B and C are controlled by the DIV_SELA, DIV_SELB and  
DIV_SELC, respectively.  
External feedback for “zero delay” clock regeneration  
Output skew, Same Frequency: 300ps (maximum)  
Output skew, Different Frequency: 400ps (maximum)  
Cycle-to-cycle jitter: 100ps (maximum)  
For test and system debug purposes, the PLL_SEL input allows  
the PLL to be bypassed. When LOW, the nMR input resets the 3.3V supply voltage  
internal dividers and forces the outputs to the high impedance  
state.  
-40°C to 85°C ambient operating temperature  
The effective fanout of the ICS87931I can be increased to 12 by  
utilizing the ability of each output to drive two series terminated  
transmission lines.  
PIN ASSIGNMENT  
32 31 30 29 28 27 26 25  
1
2
3
4
5
6
7
8
24  
23  
22  
21  
20  
19  
18  
17  
nc  
VDDA  
GND  
QB0  
ICS87931I  
POWER_DN  
CLK1  
QB1  
32-Lead LQFP  
VDDO  
7mm x 7mm x 1.4mm  
package body  
nMR  
EXTFB_SEL  
CLK_SEL  
PLL_SEL  
nc  
CLK0  
Y package  
TopView  
nCLK0  
GND  
BLOCK DIAGRAM  
9
10 11 12 13 14 15 16  
Pullup  
POWER_DN  
Pullup  
PLL_SEL  
Pulldown  
Pullup  
CLK1  
CLK_SEL  
0
Pullup  
None  
1
0
CLK0  
0
1
QA0  
QA1  
÷2/÷4  
÷2/÷4  
PHASE  
DETECTOR  
1
VCO  
÷2  
nCLK0  
Pulldown  
Pullup  
LPF  
EXTFB_SEL  
EXT_FB  
1
0
QB0  
QB1  
÷8  
Pulldown  
Pulldown  
DIV_SELA  
DIV_SELB  
Pullup  
÷4/÷6  
QC0  
QC1  
CLK_EN0  
CLK_EN1  
DIV_SELC  
DISABLE  
LOGIC  
Pullup  
Pulldown  
POWER-ON RESET  
Pullup  
nMR  
ICS87931BYI REVISION A AUGUST 25, 2010  
1
©2010 Integrated Device Technology, Inc.  

ICS87931BYILF 替代型号

型号 品牌 替代类型 描述 数据表
ICS87931BYILFT IDT

完全替代

PLL Based Clock Driver, 6 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM

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