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ICS87949AYILFT PDF预览

ICS87949AYILFT

更新时间: 2024-11-17 21:14:51
品牌 Logo 应用领域
艾迪悌 - IDT 驱动逻辑集成电路
页数 文件大小 规格书
13页 216K
描述
Low Skew Clock Driver, 87949 Series, 15 True Output(s), 0 Inverted Output(s), PQFP52, 10 X 10 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, MS-026, LQFP-52

ICS87949AYILFT 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:QFP
包装说明:LQFP, QFP52,.47SQ针数:52
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.65
系列:87949输入调节:DIFFERENTIAL MUX
JESD-30 代码:S-PQFP-G52JESD-609代码:e3
长度:10 mm逻辑集成电路类型:LOW SKEW CLOCK DRIVER
最大I(ol):0.02 A湿度敏感等级:3
功能数量:1反相输出次数:
端子数量:52实输出次数:15
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:LQFP封装等效代码:QFP52,.47SQ
封装形状:SQUARE封装形式:FLATPACK, LOW PROFILE
峰值回流温度(摄氏度):260电源:3.3 V
Prop。Delay @ Nom-Sup:10.6 ns传播延迟(tpd):10.6 ns
认证状态:Not QualifiedSame Edge Skew-Max(tskwd):0.35 ns
座面最大高度:1.6 mm子类别:Clock Drivers
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn) - annealed
端子形式:GULL WING端子节距:0.65 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
宽度:10 mm最小 fmax:160 MHz
Base Number Matches:1

ICS87949AYILFT 数据手册

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ICS87949I  
LOW SKEW, ÷1, ÷2  
CLOCK GENERATOR  
GENERAL DESCRIPTION  
FEATURES  
The ICS87949I is a low skew, ÷1, ÷2 Clock Generator. • Fifteen single ended LVCMOS outputs,  
The ICS87949I has selectable single ended clock or  
LVPECL clock inputs. The single ended clock input  
accepts LVCMOS or LVTTL input levels. The PCLK, nPCLK  
pair can accept LVPECL, CML, or SSTL input levels. The  
low impedance LVCMOS outputs are designed to drive 50Ω  
series or parallel terminated transmission lines.The  
effective fanout can be increased from 15 to 30 by utilizing  
the ability of the outputs to drive two series terminated lines.  
7Ω typical output impedance  
• Selectable LVCMOS or LVPECL clock inputs  
• CLK0 and CLK1 can accept the following input levels:  
LVCMOS and LVTTL  
• PCLK, nPCLK supports the following input types:  
LVPECL, CML, SSTL  
• Maximum output frequency: 160MHz  
• Output skew: 350ps (maximum)  
• Part-to-part skew: 2.75ns (maximum)  
• 3.3V supply voltage  
The divide select inputs, DIV_SELx, control the output  
frequency of each bank. The outputs can be utilized in the  
÷1, ÷2 or a combination of ÷1 and ÷2 modes. The master  
reset input, MR/nOE, resets the internal frequency dividers  
and also controls the active and high impedance states of  
all outputs.  
• -40°C to 85°C ambient operating temperature  
The ICS87949I is characterized at 3.3V core/3.3V output.  
Guaranteed output and part-to-part skew characteristics make  
the ICS87949I ideal for those clock distribution applications  
demanding well defined performance and repeatability.  
• Available in both standard and lead-free RoHS compliant  
packages  
BLOCK DIAGRAM  
PIN ASSIGNMENT  
CLK_SEL  
0
1
CLK0  
CLK1  
÷1  
÷2  
0
1
52 51 50 49 48 47 46 45 44 43 42 41 40  
MR/nOE  
CLK_SEL  
VDD  
1
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
nc  
2
GND  
QC0  
VDDC  
QC1  
GND  
QC2  
VDDC  
QC3  
GND  
GND  
QD5  
nc  
R
PCLK  
nPCLK  
3
0
1
4
CLK0  
QA0:QA1  
QB0:QB2  
QC0:QC3  
PCLK_SEL  
DIV_SELA  
5
CLK1  
6
PCLK  
7
ICS87949I  
nPCLK  
0
1
8
PCLK_SEL  
DIV_SELA  
DIV_SELB  
DIV_SELC  
DIV_SELD  
GND  
9
10  
11  
12  
13  
DIV_SELB  
DIV_SELC  
0
1
14 15 16 17 18 19 20 21 22 23 24 25 26  
0
1
QD0:QD5  
52-Lead LQFP  
10mm x 10mm x 1.4mm package body  
Y Package  
DIV_SELD  
MR/nOE  
Top View  
87949AYI  
www.idt.com  
REV. C AUGUST 5, 2010  
1

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