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ICS87951AYLF PDF预览

ICS87951AYLF

更新时间: 2024-09-30 20:00:39
品牌 Logo 应用领域
艾迪悌 - IDT 驱动逻辑集成电路
页数 文件大小 规格书
13页 156K
描述
PLL Based Clock Driver, 9 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, MS-026, LQFP-32

ICS87951AYLF 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:QFP
包装说明:7 X 7 MM, 1.40 MM HEIGHT, MS-026, LQFP-32针数:32
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.41输入调节:DIFFERENTIAL MUX
JESD-30 代码:S-PQFP-G32JESD-609代码:e3
长度:7 mm逻辑集成电路类型:PLL BASED CLOCK DRIVER
湿度敏感等级:3功能数量:1
反相输出次数:端子数量:32
实输出次数:9最高工作温度:70 °C
最低工作温度:输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:LQFP
封装形状:SQUARE封装形式:FLATPACK, LOW PROFILE
峰值回流温度(摄氏度):260认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.375 ns座面最大高度:1.6 mm
最大供电电压 (Vsup):3.465 V最小供电电压 (Vsup):3.135 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
温度等级:COMMERCIAL端子面层:MATTE TIN
端子形式:GULL WING端子节距:0.8 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
宽度:7 mmBase Number Matches:1

ICS87951AYLF 数据手册

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PRELIMINARY  
ICS87951  
Integrated  
Circuit  
Systems, Inc.  
LOW SKEW, 1-TO-9  
DIFFERENTIAL-TO-LVCMOS ZERO DELAY BUFFER  
FEATURES  
GENERAL DESCRIPTION  
Fully integrated PLL  
The ICS87951 is a low voltage, low skew 1-to-9  
Differential-to-LVCMOS clock generator and a  
member of the HiPerClockSfamily of High Per-  
9 single ended 3.3V LVCMOS outputs  
HiPerClockS™  
formance Clock Solutions from ICS. The Selectable single ended CLK0 or differential CLK1, nCLK1  
ICS87951 has two selectable clock inputs. The  
inputs  
single ended clock input accepts LVCMOS or LVTTL input lev-  
els. The CLK1, nCLK1 pair can accept most standard differ-  
ential input levels. With output frequencies up to 180MHz, the  
ICS87951 is targeted for high performance clock applications.  
Along with a fully integrated PLL, the ICS87951 contains fre-  
quency configurable outputs and an external feedback input  
for regenerating clocks with zero delay.  
The single ended CLK0 input can accept the following input  
levels: LVCMOS or LVTTL input levels  
CLK1, nCLK1 supports the following input types:  
LVDS, LVPECL, LVHSTL, SSTL, HCSL  
Maximum output frequency up to 180MHz  
VCO range: 200MHz to 480MHz  
External feedback for zero delayclock regeneration  
Cycle-to-cycle jitter: 100ps ꢀtypicalꢁ  
Output skew: 375ps ꢀmaximumꢁ  
PLL reference zero delay: 350ps window ꢀmaximumꢁ  
3.3V operating supply  
0°C to 70°C ambient operating temperature  
Pin compatible with the MPC951  
Industrial temperature information available upon request  
PIN ASSIGNMENT  
32 31 30 29 28 27 26 25  
VDDA  
EXT_FB  
1
2
3
4
5
6
7
8
24  
23  
22  
21  
20  
19  
18  
17  
QC0  
VDDO  
QC1  
GND  
QD0  
VDDO  
QD1  
GND  
DIV_SELA  
DIV_SELB  
DIV_SELC  
DIV_SELD  
GND  
ICS87951  
CLK1  
9
10 11 12 13 14 15 16  
32-Lead LQFP  
7mm x 7mm x 1.4mm package body  
Y package  
Top View  
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial  
product characterization. Integrated Circuit Systems, Incorporated ꢀICSꢁ reserves the right to change any circuitry or specifications without notice.  
87951AY  
www.icst.com/products/hiperclocks.html  
REV. A NOVEMBER 30, 2001  
1

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