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ICS87952AYI-147 PDF预览

ICS87952AYI-147

更新时间: 2024-11-17 20:07:59
品牌 Logo 应用领域
艾迪悌 - IDT 驱动逻辑集成电路
页数 文件大小 规格书
12页 136K
描述
PLL Based Clock Driver, 87952 Series, 11 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, MS-026BBA, LQFP-32

ICS87952AYI-147 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:QFP
包装说明:7 X 7 MM, 1.40 MM HEIGHT, MS-026BBA, LQFP-32针数:32
Reach Compliance Code:not_compliantHTS代码:8542.39.00.01
风险等级:5.85系列:87952
输入调节:STANDARDJESD-30 代码:S-PQFP-G32
长度:7 mm逻辑集成电路类型:PLL BASED CLOCK DRIVER
功能数量:1反相输出次数:
端子数量:32实输出次数:11
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:LQFP封装形状:SQUARE
封装形式:FLATPACK, LOW PROFILE传播延迟(tpd):0.2 ns
认证状态:Not QualifiedSame Edge Skew-Max(tskwd):0.15 ns
座面最大高度:1.6 mm最大供电电压 (Vsup):3.465 V
最小供电电压 (Vsup):3.135 V标称供电电压 (Vsup):3.3 V
表面贴装:YES温度等级:INDUSTRIAL
端子形式:GULL WING端子节距:0.8 mm
端子位置:QUAD宽度:7 mm
最小 fmax:180 MHzBase Number Matches:1

ICS87952AYI-147 数据手册

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ICS87952I-147  
LOW SKEW, 1-TO-11  
LVCMOS / LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER  
Integrated  
Circuit  
Systems, Inc.  
GENERAL DESCRIPTION  
FEATURES  
The ICS87952I-147 is a low voltage, low skew  
Fully integrated PLL  
ICS  
HiPerClockS™  
LVCMOS/LVTTL Clock Generator and a mem-  
Eleven LVCMOS / LVTTL outputs,  
7Ω typical output impedance  
ber of the HiPerClockS™ family of High Perfor-  
mance Clock Solutions from ICS. With output  
frequencies up to 180MHz, the ICS87952I-147  
LVCMOS / LVTTL REF_CLK input  
is targeted for high performance clock applications. Along  
with a fully integrated PLL, the ICS87952I-147 contains fre-  
quency configurable outputs and an external feedback input  
for regenerating clocks with “zero delay”.  
Output frequency range up to 180MHz at VDD = 3.3V 5ꢀ  
VCO range: 240MHz - 480MHz  
External feedback for “zero delay” clock regeneration  
Cycle-to-cycle jitter: 100ps (maximum)  
3.3V supply voltage  
For test and system debug purposes, the nPLL_EN input  
allows the PLL to be bypassed. When HIGH, the MR/nOE  
input resets the internal dividers and forces the outputs to the  
high impedance state.  
-40°C to 85°C ambient operating temperature  
The low impedance LVCMOS/LVTTL outputs of the  
ICS87952I-147 are designed to drive terminated transmis-  
sion lines.The effective fanout of each output can be doubled  
by utilizing the ability of each output to drive two series termi-  
nated transmission lines.  
Available in both standard and lead-free RoHS compliant  
packages  
BLOCK DIAGRAM  
PIN ASSIGNMENT  
nPLL_EN  
24 23 22 21 20 19 18 17  
1
0
0
1
REF_CLK  
FB_IN  
÷4/÷6  
QA0  
VDDO  
QB2  
25  
26  
27  
28  
29  
30  
31  
32  
16  
15  
14  
13  
12  
11  
10  
9
VDDO  
PHASE  
VCO  
240 - 480MHz  
÷2  
QA1  
QA2  
QA3  
QA4  
DETECTOR  
QA2  
QB3  
QA1  
GNDO  
GNDO  
QC0  
GNDO  
QA0  
LFP  
ICS87952I-147  
VCO_SEL  
F_SELA  
VDD  
QC1  
VDDA  
÷4/÷2  
QB0  
QB1  
QB2  
QB3  
VDDO  
nPLL_EN  
1
2
3
4
5
6
7
8
F_SELB  
32-Lead LQFP  
7mm x 7mm x 1.4mm package body  
÷2/÷4  
QC0  
QC1  
F_SELC  
MR/nOE  
Y package  
TopView  
87952AYI-147  
www.icst.com/products/hiperclocks.html  
REV.B APRIL 10, 2006  
1

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