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ICS87951AYI PDF预览

ICS87951AYI

更新时间: 2024-09-30 21:14:39
品牌 Logo 应用领域
SPECTRUM 驱动逻辑集成电路
页数 文件大小 规格书
13页 142K
描述
PLL Based Clock Driver, 87951 Series, 9 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 X 1.40 MM, MS-026, LQFP-32

ICS87951AYI 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:QFP
包装说明:LQFP,针数:32
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.41系列:87951
输入调节:DIFFERENTIAL MUXJESD-30 代码:S-PQFP-G32
长度:7 mm逻辑集成电路类型:PLL BASED CLOCK DRIVER
功能数量:1反相输出次数:
端子数量:32实输出次数:9
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:LQFP封装形状:SQUARE
封装形式:FLATPACK, LOW PROFILE峰值回流温度(摄氏度):NOT SPECIFIED
传播延迟(tpd):4 ns认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.75 ns座面最大高度:1.6 mm
最大供电电压 (Vsup):3.465 V最小供电电压 (Vsup):3.135 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
温度等级:INDUSTRIAL端子形式:GULL WING
端子节距:0.8 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:7 mm
最小 fmax:25 MHzBase Number Matches:1

ICS87951AYI 数据手册

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ICS87951I  
LOW SKEW, 1-TO-9  
DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY BUFFER  
Integrated  
Circuit  
Systems, Inc.  
FEATURES  
GENERAL DESCRIPTION  
Fully integrated PLL  
The ICS87951I is a low voltage, low skew 1-to-9  
ICS  
Differential-to-LVCMOS/LVTTL Cock Generator  
and a member of the HiPerClockS™family of High  
Nine single ended 3.3V LVCMOS/LVTTL outputs  
HiPerClockS™  
Performance Clock Solutions from ICS. The Selectable single ended CLK0 or differential  
ICS87951I has two selectable clock inputs. The  
CLK1, nCLK1 inputs  
single ended clock input accepts LVCMOS or LVTTL input  
levels.The CLK1, nCLK1 pair can accept most standard differ-  
ential input levels. With output frequencies up to 180MHz, the  
ICS87951I is targeted for high performance clock applications.  
Along with a fully integrated PLL, the ICS87951I contains fre-  
quency configurable outputs and an external feedback input for  
regenerating clocks with “zero delay”.  
The single ended CLK0 input can accept the following  
input levels: LVCMOS or LVTTL input levels  
CLK1, nCLK1 supports the following input types:  
LVDS, LVPECL, LVHSTL, SSTL, HCSL  
Output frequency range: 25MHz to 180MHz  
VCO range: 200MHz to 480MHz  
External feedback for ”zero delay” clock regeneration  
Cycle-to-cycle jitter: 100ps ꢀtypicalꢁ  
Output skew: 375ps ꢀmaximumꢁ  
PLL reference zero delay: 350ps window ꢀmaximumꢁ  
3.3V operating supply  
-40°C to 85°C ambient operating temperature  
Available in both standard and lead-free RoHS-compliant  
packages  
PIN ASSIGNMENT  
32 31 30 29 28 27 26 25  
VDDA  
EXT_FB  
DIV_SELA  
DIV_SELB  
DIV_SELC  
DIV_SELD  
GND  
1
2
3
4
5
6
7
8
24  
23  
22  
21  
20  
19  
18  
17  
QC0  
VDDO  
QC1  
GND  
QD0  
VDDO  
QD1  
GND  
ICS87951I  
CLK1  
9
10 11 12 13 14 15 16  
32-Lead LQFP  
7mm x 7mm x 1.4mm package body  
Y package  
TopView  
87951AYI  
www.icst.com/products/hiperclocks.html  
REV.B NOVEMBER 23, 2005  
1

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