Datasheet > ICS87946-01

ICS87946-01

更新时间： 2024-11-17 04:44:23

品牌	Logo	应用领域
矽成 - ICSI		时钟发生器
页数	文件大小	规格书
13页	159K
描述
LVPECL-TO-LVCMOS/LVTTL CLOCK GENERATOR

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中文翻译

获取价格

数据手册

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ICS87946-01 数据手册

PRELIMINARY

ICS87946-01

Integrated

Circuit

Systems, Inc.

LOW SKEW ÷1, ÷2

LVPECL-TO-LVCMOS/LVTTLCLOCK GENERATOR

GENERAL DESCRIPTION

FEATURES

The ICS87946-01 is a low skew, ÷1, ÷2 Clock • 10 single ended LVCMOS outputs, 7Ω typical output

Generator and a member of the HiPerClockS™

family of High Performance Clock Solutions from

ICS. The ICS87946-01 has one LVPECL clock

input pair. The PCLK, nPCLK pair can accept

impedance

HiPerClockS™

• LVPECLclock input pair

• PCLK, nPCLK supports the following input levels:

LVPECL, CML, SSTL

LVPECL, CML, or SSTL input levels. The low impedance

LVCMOS outputs are designed to drive 50Ω series or parallel

terminated transmission lines. The effective fanout can be in-

creased from 10 to 20 by utilizing the ability of the outputs to

drive two series terminated lines.

• Maximum input frequency: 250MHz

• Output skew: 200ps (maximum)

• Part-to-part skew: 500ps (typical)

The divide select inputs, DIV_SELx, control the output fre-

quency of each bank. The outputs can be utilized in the ÷1,

÷2 or a combination of ÷1 and ÷2 modes. The master reset

input, MR/nOE, resets the internal frequency dividers and also

controls the active and high impedance states of all outputs.

• Multiple frequency skew: 350ps (maximum)

• 3.3V input, outputs may be either 3.3V or 2.5V supply modes

• 0°C to 70°C ambient operating temperature

• Industrial temperature information available upon request

The ICS87946-01 is characterized at 3.3V core/3.3V output

and 3.3V core/2.5V output. Guaranteed bank, output and part-

to-part skew characteristics make the ICS87946-01 ideal for

those clock distribution applications demanding well defined

performance and repeatability.

BLOCK DIAGRAM

PIN ASSIGNMENT

÷1

÷2

PCLK

nPCLK

QA0 - QA2

QB0 - QB2

QC0 - QC3

32 31 30 29 28 27 26 25

V^DD

DIV_SELA

DIV_SELB

GND

QB0

V^DDB

QB1

GND

QB2

V^DDB

VDDC

PCLK

nPCLK

ICS87946-01

DIV_SELA

DIV_SELB

DIV_SELC

GND

DIV_SELC

MR/nOE

10 11 12 13 14 15 16

32-Lead LQFP

7mm x 7mm x 1.4mm

Y Package

Top View

The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial

product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.

87946AY-01

www.icst.com/products/hiperclocks.html

REV. A JANUARY 2, 2002

12 3 4 5 6 7...13

中文翻译

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与ICS87946-01相关器件

型号	品牌	获取价格	描述	数据表
ICS87946AY-01	ICSI	获取价格	LVPECL-TO-LVCMOS/LVTTL CLOCK GENERATOR
ICS87946AY-01LF	IDT	获取价格	Low Skew Clock Driver, 10 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM
ICS87946AY-01LFT	IDT	获取价格	Low Skew Clock Driver, 10 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM
ICS87946AY-01T	ICSI	获取价格	LVPECL-TO-LVCMOS/LVTTL CLOCK GENERATOR
ICS87946AYI-147LF	IDT	获取价格	Low Skew Clock Driver, 10 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM
ICS87946AYI-147LFT	IDT	获取价格	Low Skew Clock Driver, 10 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM
ICS87946AYI-147T	IDT	获取价格	Low Skew Clock Driver, 10 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM
ICS87946AYILF	IDT	获取价格	Low Skew Clock Driver, 10 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM
ICS87946AYILFT	IDT	获取价格	Low Skew Clock Driver, 10 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM
ICS87949-01	ICSI	获取价格	LOW SKEW ±1, ±2 CLOCK GENERATOR

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