PRELIMINARY
ICS87949-01
Integrated
Circuit
Systems, Inc.
LOW SKEW
÷1, ÷2
CLOCK GENERATOR
GENERAL DESCRIPTION
FEATURES
The ICS87949-01 is a low skew, ÷1, ÷2 Clock • 15 single ended LVCMOS outputs, 7Ω typical output
,&6
Generator and a member of the HiPerClockS™
family of High Performance Clock Solutions from
ICS. The ICS87949-01 has selectable single
ended clock or LVPECL clock inputs. The single
impedance
HiPerClockS™
• Selectable LVCMOS or LVPECL clock inputs
• CLK0 and CLK1 can accept the following input levels:
LVCMOS and LVTTL
ended clock input accepts LVCMOS or LVTTL input levels.
The PCLK, nPCLK pair can accept LVPECL, CML, or SSTL
input levels. The low impedance LVCMOS outputs are de-
signed to drive 50Ω series or parallel terminated transmis-
sion lines. The effective fanout can be increased from 15 to
30 by utilizing the ability of the outputs to drive two series
terminated lines.
• PCLK, nPCLK supports the following input types:
LVPECL, CML, SSTL
• Maximum input frequency: 250MHz
• Output skew: 200ps (maximum)
• Part-to-part skew: 500ps (typical)
The divide select inputs, DIV_SELx, control the output frequency
of each bank. The outputs can be utilized in the ÷1, ÷2 or a
combination of ÷1 and ÷2 modes. The master reset input, MR/
nOE, resets the internal frequency dividers and also controls
the active and high impedance states of all outputs.
• Multiple frequency skew: 350ps (maximum)
• 3.3V input, outputs may be either 3.3V or 2.5V supply modes
• 0°C to 70°C ambient operating temperature
• Industrial temperature information available upon request
The ICS87949-01 is characterized at 3.3V core/3.3V output and
3.3V core/ 2.5V output. Guaranteed bank, output and part-to-
part skew characteristics make the ICS87949-01 ideal for those
clock distribution applications demanding well defined perfor-
mance and repeatability.
• Functionally compatible to the MPC949 in a smaller footprint
requiring less board space
BLOCK DIAGRAM
PIN ASSIGNMENT
CLK_SEL
0
1
CLK0
CLK1
÷1
÷2
0
1
48 47 46 45 44 43 42 41 40 39 38 37
1
36
35
34
33
32
31
30
29
28
27
26
25
MR/nOE
CLK_SEL
VDD
nc
R
PCLK
nPCLK
2
GND
QC0
VDDC
QC1
GND
QC2
VDDC
QC3
GND
GND
QD5
3
0
1
4
CLK0
QA0 - QA1
QB0 - QB2
QC0 - QC3
PCLK_SEL
DIV_SELA
5
CLK1
6
PCLK
ICS87949-01
7
nPCLK
0
1
8
PCLK_SEL
DIV_SELA
DIV_SELB
DIV_SELC
DIV_SELD
9
10
11
12
DIV_SELB
DIV_SELC
0
1
13 14 15 16 17 18 19 20 21 22 23 24
0
1
QD0 - QD5
48-Lead LQFP
7mm x 7mm x 1.4mm package body
DIV_SELD
MR/nOE
Y Package
Top View
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
87949AY-01
www.icst.com/products/hiperclocks.html
REV. A JANUARY 2, 2002
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