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ICS87931BYIT

更新时间: 2024-09-29 22:09:31
品牌 Logo 应用领域
矽成 - ICSI 时钟
页数 文件大小 规格书
14页 166K
描述
LOW SKEW, 1-TO-6 LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER

ICS87931BYIT 数据手册

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ICS87931I  
LOW SKEW, 1-TO-6  
LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER  
Integrated  
Circuit  
Systems, Incꢀ  
GENERAL DESCRIPTION  
FEATURES  
The ICS87931I is a low voltage, low skew  
Fully integrated PLL  
LVCMOS/LVTTL Clock Multiplier/Zero Delay  
6 LVCMOS/LVTTLoutputs, 7typical output impedance  
HiPerClockS™  
Buffer and a member of the HiPerClockS™ family  
of High Performance Clock Solutions from ICS.  
With output frequencies up to 150MHz, the  
Selectable differential CLK0, nCLK0 or LVCMOS/LVTTLclock  
for redundant clock applications  
ICS87931I is targeted for high performance clock applications.  
Along with a fully integrated PLL, the ICS87931I contains fre-  
quency configurable outputs and an external feedback input for  
regenerating clocks with “zero delay”.  
Maximum output frequency: 150MHz  
VCO range: 220MHz to 480MHz  
External feedback for “zero delay” clock regeneration  
Output skew, Same Frequency: 300ps (maximum)  
Output skew, Different Frequency: 400ps (maximum)  
Cycle-to-cycle jitter: 100ps (maximum)  
3.3V supply voltage  
Selectable clock inputs, CLK1 and differential CLK0, nCLK0  
support redundant clock applications. The CLK_SEL input de-  
termines which reference clock is used. The output divider val-  
ues of Bank A, B and C are controlled by the DIV_SELA,  
DIV_SELB and DIV_SELC, respectively.  
-40°C to 85°C ambient operating temperature  
Pin compatible with MPC931  
For test and system debug purposes, the PLL_SEL input al-  
lows the PLL to be bypassed. When LOW, the nMR input re-  
sets the internal dividers and forces the outputs to the high im-  
pedance state.  
PIN ASSIGNMENT  
The effective fanout of the ICS87931I can be increased to 12  
by utilizing the ability of each output to drive two series termi-  
nated transmission lines.  
32 31 30 29 28 27 26 25  
1
2
3
4
5
6
7
8
24  
23  
22  
21  
20  
19  
18  
17  
nc  
VDDA  
GND  
QB0  
ICS87931I  
POWER_DN  
CLK1  
QB1  
32-Lead LQFP  
VDDO  
7mm x 7mm x 1.4mm  
package body  
nMR  
EXTFB_SEL  
CLK_SEL  
PLL_SEL  
nc  
CLK0  
Y package  
Top View  
nCLK0  
GND  
9
10 11 12 13 14 15 16  
BLOCK DIAGRAM  
POWER_DN  
Pullup  
Pullup  
PLL_SEL  
Pulldown  
Pullup  
CLK1  
CLK_SEL  
0
1
Pullup  
None  
1
0
CLK0  
0
QA0  
QA1  
÷2/÷4  
÷2/÷4  
PHASE  
DETECTOR  
VCO  
÷2  
nCLK0  
1
Pulldown  
Pullup  
LPF  
EXTFB_SEL  
EXT_FB  
1
0
QB0  
QB1  
÷8  
Pulldown  
Pulldown  
DIV_SELA  
DIV_SELB  
Pullup  
÷4/÷6  
QC0  
QC1  
CLK_EN0  
CLK_EN1  
DIV_SELC  
DISABLE  
LOGIC  
Pullup  
Pulldown  
POWER-ON RESET  
Pullup  
nMR  
87931BYI  
www.icst.com/products/hiperclocks.html  
REV. A JUNE 23, 2003  
1

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