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ICS853S314AGILF PDF预览

ICS853S314AGILF

更新时间: 2024-11-11 21:21:59
品牌 Logo 应用领域
艾迪悌 - IDT 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
16页 290K
描述
Low Skew Clock Driver, 853S Series, 4 True Output(s), 0 Inverted Output(s), PDSO20, 4.40 MM X 6.50 MM, 0.925 MM HEIGHT, ROHS COMPLIANT, MO-153, TSSOP-20

ICS853S314AGILF 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:TSSOP
包装说明:4.40 MM X 6.50 MM, 0.925 MM HEIGHT, ROHS COMPLIANT, MO-153, TSSOP-20针数:20
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.82其他特性:IT ALSO OPERATE ON 3.3V SUPPLY
系列:853S输入调节:DIFFERENTIAL
JESD-30 代码:R-PDSO-G20JESD-609代码:e3
长度:6.5 mm逻辑集成电路类型:LOW SKEW CLOCK DRIVER
湿度敏感等级:1功能数量:1
反相输出次数:端子数量:20
实输出次数:4最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP20,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):260电源:2.5/3.3 V
认证状态:Not QualifiedSame Edge Skew-Max(tskwd):0.05 ns
座面最大高度:1.2 mm子类别:Clock Drivers
最大供电电压 (Vsup):2.625 V最小供电电压 (Vsup):2.375 V
标称供电电压 (Vsup):2.5 V表面贴装:YES
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn) - annealed
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:4.4 mm最小 fmax:2700 MHz
Base Number Matches:1

ICS853S314AGILF 数据手册

 浏览型号ICS853S314AGILF的Datasheet PDF文件第2页浏览型号ICS853S314AGILF的Datasheet PDF文件第3页浏览型号ICS853S314AGILF的Datasheet PDF文件第4页浏览型号ICS853S314AGILF的Datasheet PDF文件第5页浏览型号ICS853S314AGILF的Datasheet PDF文件第6页浏览型号ICS853S314AGILF的Datasheet PDF文件第7页 
LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-2.5V,  
3.3V LVPECL/ECL FANOUT BUFFER  
ICS853S314I  
GENERAL DESCRIPTION  
FEATURES  
The ICS853S314I is a low skew 1-to-4 Differential  
Four differential ECL/LVPECL level outputs  
ICS  
HiPerClockS™  
Fanout Buffer, designed with clock distribution in  
mind, accepting two clock sources into an input  
MUX. The MUX is controlled by a CLK_SEL pin.  
This makes the ICS853S314I very versatile, in that,  
One differential ECL/LVPECL or single-ended input (CLKA)  
One differential HSTL or single-ended input (CLKB)  
Maximum output frequency: 2.7GHz  
it can operate as both a differential clock buffer as well as a  
signal-level translator and fanout buffer.  
Additive phase jitter, RMS: 0.138ps (typical) @ 156.25MHz,  
Output skew: 50ps (maximum)  
The device is designed on a SiGe process and can operate at  
frequencies in excess of 2.7GHz. This ensures negligible jitter  
introduction to the timing budget which makes it an ideal choice  
for distributing high frequency, high precision clocks across  
back planes and boards in communication systems. Internal  
temperature compensation guarantees consistent performance  
across various platforms.  
Part-to-part skew: 150ps (maximum)  
LVPECL and HSTL mode operating voltage supply range:  
VCC = 2.5V 5ꢀ or 3.3V 5ꢀ, VEE = 0V  
ECL mode operating voltage supply range:  
VEE = -3.3V 5ꢀ or -2.5V 5ꢀ, VCC = 0V  
-40°C to 85°C ambient operating temperature  
Available in both standard (RoHS 5) and lead-free (RoHS 6)  
packages  
BLOCK DIAGRAM  
PIN ASSIGNMENT  
VCC  
Q0  
VCC  
VCC  
Q0  
nQ0  
Q1  
nQ1  
Q2  
nQ2  
Q3  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
CLKA  
nQ0  
nc  
VCC  
nCLKA  
Q1  
nQ1  
CLK_SEL  
CLKA  
nCLKA  
CLKB  
nCLKB  
VEE  
0
VCC  
VEE  
Q2  
nQ2  
1
CLKB  
nCLKB  
nQ3  
VCC  
Q3  
nQ3  
VCC  
VEE  
CLK_SEL  
ICS853S314I  
20-Lead, 209-MIL SSOP  
5.30mm x 7.20mm x 1.75mm body package  
F Package  
VEE  
Top View  
20-Lead TSSOP  
4.4mm x 6.5mm x 0.925mm body package  
G Package  
Top View  
IDT/ ICS3.3V, 2.5V LVPECL/ECL FANOUT BUFFER  
1
ICS853S314AFI REV. A JANUARY 24, 2009  

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