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ICS854057AGT PDF预览

ICS854057AGT

更新时间: 2024-11-12 07:25:39
品牌 Logo 应用领域
艾迪悌 - IDT 光电二极管
页数 文件大小 规格书
13页 256K
描述
Low Skew Clock Driver, 854057 Series, 1 True Output(s), 0 Inverted Output(s), PDSO20, 4.40 X 6.50 MM, 0.925 MM HEIGHT, MO-153, TSSOP-20

ICS854057AGT 数据手册

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ICS854057  
4:1 OR 2:1 LVDS CLOCK MULTIPLEXER  
WITH INTERNAL INPUT TERMINATION  
Integrated  
Circuit  
Systems, Inc.  
GENERAL DESCRIPTION  
FEATURES  
The ICS854057 is a 4:1 or 2:1 LVDS Clock Mul- High speed differential multiplexer.The device can be  
ICS  
tiplexer which can operate up to 2GHz and is a  
member of the HiPerClockSfamily of High Per-  
formance Clock Solutions from ICS.The PCLK,  
nPCLK pairs can accept most standard differen-  
configured as either a 4:1 or 2:1 multiplexer  
HiPerClockS™  
Single LVDS output  
4 selectable PCLK, nPCLK inputs with internal termination  
tial input levels. Internal termination is provided on each dif-  
ferential input pair.The ICS854057 operates using a 2.5V sup-  
ply voltage. The fully differential architecture and low propa-  
gation delay make it ideal for use in high speed multiplexing  
applications.The select pins have internal pulldown resistors.  
Leaving one input unconnected (pulled to logic low by the in-  
ternal resistor) will transform the device into a 2:1 multiplexer.  
The SEL1 pin is the most significant bit and the binary num-  
ber applied to the select pins will select the same numbered  
data input (i.e., 00 selects PCLK0, nPCLK0).  
PCLK, nPCLK pairs can accept the following differential  
input levels: LVPECL, LVDS, CML, SSTL  
Output frequency: >2GHz  
Part-to-part skew: 200ps (maximum)  
Propagation delay: 800ps (maximum)  
Additive phase jitter, RMS: 66fs (typical)  
2.5V operating supply  
-40°C to 85°C ambient operating temperature  
Available in both, Standard and RoHS/Lead-Free compliant  
packages  
BLOCK DIAGRAM  
PIN ASSIGNMENT  
VT0  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
VDD  
PCLK0  
VT0  
nPCLK0  
SEL1  
SEL0  
PCLK1  
VT1  
1
2
3
4
5
6
7
8
9
VDD  
PCLK3  
VT3  
nPCLK3  
Q
nQ  
PCLK2  
VT2  
nPCLK2  
GND  
50  
PCLK0  
50  
nPCLK0  
VT1  
50  
50  
nPCLK1  
PCLK1  
nPCLK1  
GND 10  
00  
01  
10  
11  
ICS854057  
VT2  
Q
nQ  
20-LeadTSSOP  
4.40mm x 6.50mm x 0.925mm body package  
G Package  
50  
50  
50  
PCLK2  
nPCLK2  
TopView  
VT3  
50  
PCLK3  
nPCLK3  
Pulldown  
Pulldown  
SEL1  
SEL0  
854057AG  
www.icst.com/products/hiperclocks.html  
REV. A JULY 18, 2005  
1

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