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ICS854054AGLF PDF预览

ICS854054AGLF

更新时间: 2024-11-11 03:59:55
品牌 Logo 应用领域
矽成 - ICSI 复用器逻辑集成电路光电二极管时钟
页数 文件大小 规格书
13页 200K
描述
DIFFERENTIAL-TO-LVDS CLOCK MULTIPLEXER

ICS854054AGLF 数据手册

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ICS854054  
4:1  
DIFFERENTIAL-TO-LVDS CLOCK MULTIPLEXER  
Integrated  
Circuit  
Systems, Inc.  
GENERAL DESCRIPTION  
FEATURES  
The ICS854054 is a 4:1 Differential-to-LVDS Clock High speed 4:1 differential multiplexer  
ICS  
HiPerClockS™  
Multiplexer which can operate up to 2.8GHz and  
is a member of the HiPerClockSfamily of High  
Performance Clock Solutions from ICS. The  
ICS854054 has 4 selectable differential clock  
One differential LVDS output  
Four selectable differential clock inputs  
PCLKx, nPCLKx pairs can accept the following  
differential input levels: LVPECL, LVDS, CML, SSTL  
inputs. The PCLK, nPCLK input pairs can accept LVPECL,  
LVDS, CML or SSTL levels. The fully differential architec-  
ture and low propagation delay make it ideal for use in clock  
distribution circuits. The select pins have internal pulldown  
resistors. The SEL1 pin is the most significant bit and the  
binary number applied to the select pins will select the same  
numbered data input (i.e., 00 selects PCLK0, nPCLK0).  
Maximum output frequency: 2.8GHz  
Translates any single ended input signal to  
LVDS levels with resistor bias on nPCLKx input  
Part-to-part skew: 375ps (maximum)  
Propagation delay: 700ps (maximum)  
Supply voltage range: 3.135V to 3.465V  
-40°C to 85°C ambient operating temperature  
Available in both standard and lead-free RoHS compliant  
packages  
BLOCK DIAGRAM  
PIN ASSIGNMENT  
1
2
3
4
5
6
7
8
PCLK0  
nPCLK0  
PCLK1  
nPCLK1  
VDD  
SEL0  
SEL1  
GND  
16  
15  
14  
13  
12  
11  
10  
9
VDD  
Q
nQ  
GND  
nPCLK3  
PCLK3  
nPCLK2  
PCLK2  
PCLK0  
nPCLK0  
(default)  
00  
01  
10  
PCLK1  
nPCLK1  
Q
nQ  
PCLK2  
nPCLK2  
ICS854054  
16-LeadTSSOP  
PCLK3  
nPCLK3  
4.4mm x 5.0mm x 0.92mm package body  
G Package  
11  
TopView  
SEL0  
SEL1  
854054AG  
www.icst.com/products/hiperclocks.html  
REV.A MARCH 29, 2006  
1

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