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ICS375G-XXT PDF预览

ICS375G-XXT

更新时间: 2024-11-14 18:51:15
品牌 Logo 应用领域
艾迪悌 - IDT 时钟光电二极管外围集成电路晶体
页数 文件大小 规格书
5页 69K
描述
Clock Generator, 200MHz, CMOS, PDSO16, TSSOP-16

ICS375G-XXT 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:TSSOP
包装说明:TSSOP,针数:16
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.92
JESD-30 代码:R-PDSO-G16JESD-609代码:e0
长度:5 mm湿度敏感等级:1
端子数量:16最高工作温度:70 °C
最低工作温度:最大输出时钟频率:200 MHz
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):240主时钟/晶体标称频率:27 MHz
认证状态:Not Qualified座面最大高度:1.2 mm
最大供电电压:3.46 V最小供电电压:3.13 V
标称供电电压:3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:20宽度:4.4 mm
uPs/uCs/外围集成电路类型:CLOCK GENERATOR, OTHERBase Number Matches:1

ICS375G-XXT 数据手册

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PRELIMINARY INFORMATION  
ICS375  
Quad PLL with VCXO  
Quick Turn Clock Synthesizer  
Features  
Description  
The ICS375 QTClock™ generates up to 4 high quality, high  
frequency clock outputs. It is designed to replace a VCXO,  
crystals, and crystal oscillators in most electronic systems.  
The ICS375 contains a One Time Programmable (OTP) ROM,  
factory programmed with PLL divider values to output a  
broad range of frequencies (up to 200 MHz). Quick Turn  
factory programming allows customer sample requests to be  
shipped in 1-3 days. Programming features include a  
selectable frequency table and two banks of up to 2 low-  
skew outputs.  
• Packaged in 16 pin TSSOP  
• Quick turn frequency programming allows  
samples as quickly as one day  
• Two banks, up to 2 outputs each, can be low-skew  
• Can include 4 selectable output frequencies  
• Up to 2 reference outputs  
• Replaces a VCXO plus multiple crystals and  
oscillators  
• Output frequencies up to 200 MHz at 3.3 V  
• Input crystal frequency of 13 - 27 MHz  
• Duty cycle of 45/55  
Using ICS’ patented VCXO and Phase-Locked-Loop (PLL)  
techniques, the device runs from a pullable crystal. It can  
replace a VCXO and multiple crystals and oscillators, saving  
board space and cost.  
• Operating voltage of 3.3 V  
• Advanced, low power CMOS process  
Block Diagram  
OTP  
ROM  
with PLL  
Divider  
Values  
3
PLL A  
PLL B  
S2:S0  
CLK1  
Divide  
Logic  
and  
Output  
Control  
CLK2  
CLK3  
PLL C  
PLL D  
Vin  
13-27 MHz  
Pullable  
Crystal  
X1  
Voltage  
Controlled  
Crystal  
Oscillator  
CLK4  
X2  
External capacitors may be required.  
PDTS  
MDS 375 A  
1
Revision 050401  
Integrated Circuit Systems, Inc. • 525 Race Street, San Jose, CA, 95126 • (408) 295-9800 • www.icst.com  

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