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ICS388R-XXT-LF PDF预览

ICS388R-XXT-LF

更新时间: 2024-11-14 14:33:55
品牌 Logo 应用领域
艾迪悌 - IDT 时钟光电二极管外围集成电路晶体
页数 文件大小 规格书
5页 72K
描述
Clock Generator, 200MHz, CMOS, PDSO20, 0.150 INCH, SSOP-20

ICS388R-XXT-LF 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:SSOP
包装说明:SSOP,针数:20
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.84
JESD-30 代码:R-PDSO-G20JESD-609代码:e3
长度:8.65 mm端子数量:20
最高工作温度:70 °C最低工作温度:
最大输出时钟频率:200 MHz封装主体材料:PLASTIC/EPOXY
封装代码:SSOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, SHRINK PITCH峰值回流温度(摄氏度):260
主时钟/晶体标称频率:50 MHz认证状态:Not Qualified
座面最大高度:1.75 mm最大供电电压:5.5 V
最小供电电压:3.13 V标称供电电压:3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Matte Tin (Sn)
端子形式:GULL WING端子节距:0.635 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:3.9 mmuPs/uCs/外围集成电路类型:CLOCK GENERATOR, OTHER
Base Number Matches:1

ICS388R-XXT-LF 数据手册

 浏览型号ICS388R-XXT-LF的Datasheet PDF文件第2页浏览型号ICS388R-XXT-LF的Datasheet PDF文件第3页浏览型号ICS388R-XXT-LF的Datasheet PDF文件第4页浏览型号ICS388R-XXT-LF的Datasheet PDF文件第5页 
ICS388  
Quad PLL Quick Turn Clock Synthesizer  
Description  
Features  
• Packaged as 20 pin SSOP (QSOP)  
• Quick turn frequency programming allows  
samples as quickly as one day  
The ICS388 QTClock™ generates up to 9 high quality,  
high frequency clock outputs including a reference  
from a low frequency crystal or clock input. It is designed  
to replace crystals and crystal oscillators in most  
electronic systems. The ICS388 contains a One Time  
Programmable (OTP) ROM which is factory programmed  
with PLL divider values to output a broad range of  
frequencies up to 200 MHz, allowing customer  
requests for different frequencies to be shipped in 1-3  
days. Programming features include a selectable  
frequency table and up to 4 low-skew outputs.  
• Up to 4 outputs can be low-skew  
• Can include 8 selectable output frequencies  
• Up to 5 reference outputs  
• Replaces multiple crystals and oscillators  
• Output frequencies up to 200 MHz at 3.3V  
• Input crystal frequency of 5 - 27 MHz  
• Input clock frequency of 2 - 50 MHz  
• Duty cycle of 45/55  
Using Phase-Locked-Loop (PLL) techniques, the  
device runs from a standard fundamental mode,  
inexpensive crystal, or clock. It can replace multiple  
crystals and oscillators, saving board space and cost.  
• Operating voltages of 3.3 V or 5 V  
• Advanced, low power CMOS process  
Block Diagram  
CLK1  
CLK2  
OTP  
3
ROM  
with PLL  
Divider  
Values  
S2:S0  
PLLA  
Divide  
Logic  
and  
Output  
Control  
CLK3  
CLK4  
CLK5  
CLK6  
CLK7  
PLLB  
PLLC  
PLLD  
Crystal  
or clock  
input  
X1/ICLK  
Crystal  
Oscillator  
CLK8  
CLK9  
X2  
PDTS (all outputs and PLLs)  
Capacitors are required with a crystal input.  
MDS 388 B  
1
Revision 051801  
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose •CA•95126•(408) 295-9800tel • www.icst.com  

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