Datasheet > ICS3840BLF

ICS3840BLF

更新时间： 2024-11-14 11:14:27

品牌	Logo	应用领域
矽成 - ICSI		动态存储器双倍数据速率
页数	文件大小	规格书
7页	131K
描述
DDR SDRAM MUX

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ICS3840BLF 数据手册

ICS83840B

Integrated

Circuit

Systems, Inc.

DDR SDRAM MUX

GENERAL DESCRIPTION

FEATURES

The ICS83840B is a DDR SDRAM MUX and is

• 40 low skew single-ended DIMM ports

• 4 SSTL-2 compatible enable inputs

• Maximum Switching Speed: 3ns

• Output skew: 120ps (maximum)

• Bank skew: 60ps (maximum)

• r_on= 8Ω (typical)

ICS

a member of the HiPerClockS™ family of High

Performance Clock Solutions from ICS.The de-

vice has 10 Host Lines and each host line can

be passed to 4 Data Ports.The 10 channels are

allocated as follows in the DDR SDRAM appli-

HiPerClockS™

cation: 8 data lines, 1 strobe line and 1 DQm line. The Host/

Data Ports are compatible with single-ended SSTL-2 and the

device operates from a 2.5V supply.

• Full 2.5V supply modes

Guaranteed low output skew makes the ICS83840B ideal • 0°C to 70°C ambient operating temperature

for demanding applications which require well defined per-

formance and repeatability.

• Pin compatible with the CBTV4010

SIMPLIFIED SCHEMATIC

LOGIC DIAGRAM

R_ON

HP0

0DP0

1DP0

2DP0

3DP0

HPx

nDPx

400Ω

R_ON

HP9

0DP9

1DP9

2DP9

3DP9

nSn

nS0

nS1

nS2

nS3

PIN ASSIGNMENT

V_DD

nS2

nS1

1DP0

0DP0

2DP0

3DP0

0DP1

2DP1

HP1

3DP1 0DP2

V_DD

nS0

GND

HP0

1DP1

GND

HP2

1DP2

2DP2

nS3

ICS83840B

GND

3DP9

HP9

3DP8

2DP8

HP8

GND

2DP7

3DP2

0DP3

HP3

64-Ball TFBGA

2DP9

1DP9

0DP9

1DP3

2DP3

3DP3

7mm x 7mm x 1.2mm

package body

GND

0DP4

HP4

H Package

Top View

1DP8

0DP8

3DP7

1DP4

2DP4

0DP5

HP7

0DP7

3DP6

2DP6

HP6

GND

3DP5

HP5

3DP4

1DP5

1DP7

1DP6

0DP6

2DP5

83840BH

www.icst.com/products/hiperclocks.html

REV. A JANUARY 30, 2004

12 3 4 5 6 7

中文翻译

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