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ICS377R-XX-LF PDF预览

ICS377R-XX-LF

更新时间: 2024-11-14 20:42:47
品牌 Logo 应用领域
艾迪悌 - IDT 时钟光电二极管外围集成电路晶体
页数 文件大小 规格书
5页 73K
描述
Clock Generator, 200MHz, CMOS, PDSO28, 0.150 INCH, QSOP-28

ICS377R-XX-LF 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:SSOP,针数:28
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.84
JESD-30 代码:R-PDSO-G28JESD-609代码:e3
长度:9.9 mm端子数量:28
最高工作温度:70 °C最低工作温度:
最大输出时钟频率:200 MHz封装主体材料:PLASTIC/EPOXY
封装代码:SSOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, SHRINK PITCH峰值回流温度(摄氏度):260
主时钟/晶体标称频率:27 MHz认证状态:Not Qualified
座面最大高度:1.75 mm最大供电电压:3.46 V
最小供电电压:3.13 V标称供电电压:3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Matte Tin (Sn)
端子形式:GULL WING端子节距:0.635 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:3.9 mmuPs/uCs/外围集成电路类型:CLOCK GENERATOR, OTHER
Base Number Matches:1

ICS377R-XX-LF 数据手册

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PRELIMINARY INFORMATION  
ICS377  
Quad PLL with VCXO  
Quick Turn Clock Synthesizer  
Features  
Description  
The ICS377 QTClock™ generates up to 8 high quality,  
high frequency clock outputs. It is designed to replace  
a VCXO, crystals, and crystal oscillators in most  
electronic systems. The ICS377 contains a One Time  
Programmable (OTP) ROM, factory programmed with  
PLL divider values to output a broad range of  
frequencies (up to 200 MHz). Quick Turn factory  
programming allows customer sample requests to be  
shipped in 1-3 days. Programming features include a  
selectable frequency table and two banks of up to 4  
low-skew outputs.  
• Packaged in 28 pin SSOP (QSOP)  
• Quick turn frequency programming allows  
samples as quickly as one day  
• Two banks, up to 4 outputs each, can be low-skew  
• Can include 8 selectable output frequencies  
• Up to 4 reference outputs  
• Replaces a VCXO plus multiple crystals and  
oscillators  
• Output frequencies up to 200 MHz at 3.3 V  
• Input crystal frequency of 13 - 27 MHz  
• Duty cycle of 45/55  
Using ICS’ patented VCXO and Phase-Locked-Loop  
(PLL) techniques, the device runs from a pullable  
crystal. It can replace a VCXO and multiple crystals and  
oscillators, saving board space and cost.  
• Operating voltage of 3.3 V  
• Advanced, low power CMOS process  
Block Diagram  
OTP  
CLK1  
3
ROM  
with PLL  
Divider  
Values  
PLL A  
PLL B  
S2:S0  
CLK2  
Divide  
Logic  
and  
CLK3  
Output  
Control  
CLK4  
PLL C  
PLL D  
Vin  
CLK5  
CLK6  
CLK7  
CLK8  
13-27 MHz  
Pullable  
Crystal  
X1  
Voltage  
Controlled  
Crystal  
Oscillator  
X2  
External capacitors may be required.  
PDTS  
MDS 377 B  
1
Revision 050401  
Integrated Circuit Systems, Inc. • 525 Race Street, San Jose, CA, 95126 • (408) 295-9800 • www.icst.com  

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