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ICS3771G-18 PDF预览

ICS3771G-18

更新时间: 2024-11-14 15:34:35
品牌 Logo 应用领域
艾迪悌 - IDT 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
8页 175K
描述
PLL Based Clock Driver, 3771 Series, 4 True Output(s), 0 Inverted Output(s), CMOS, PDSO16, 0.40 MM, 0.65 MM PITCH, MO-153, TSSOP-28

ICS3771G-18 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:TSSOP
包装说明:TSSOP,针数:16
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.92系列:3771
输入调节:STANDARDJESD-30 代码:R-PDSO-G16
JESD-609代码:e0长度:5 mm
逻辑集成电路类型:PLL BASED CLOCK DRIVER湿度敏感等级:1
功能数量:1反相输出次数:
端子数量:16实输出次数:4
最高工作温度:70 °C最低工作温度:
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):240认证状态:Not Qualified
座面最大高度:1.2 mm最大供电电压 (Vsup):3.465 V
最小供电电压 (Vsup):3.135 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:TIN LEAD
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:20
宽度:4.4 mmBase Number Matches:1

ICS3771G-18 数据手册

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DATASHEET  
DTV, STB CLOCK SOURCE  
ICS3771-18  
Description  
Features  
The ICS3771-18 provides clock generation and  
conversion for clock rates commonly needed in HDTV  
digital video equipment. The ICS3771-18 uses the  
latest PLL technology to provide excellent phase noise  
and long term jitter performance for superior  
synchronization and S/N ratio.  
Integrated Phase-Lock Loop  
Low jitter, high accuracy outputs  
3.3 V operation  
Packaged in 16-pin TSSOP  
RoHS 6 (green and lead free) compliant packaging  
Exact (0 ppm) multiplication ratios  
For audio sampling clocks generated from 27 MHz, use  
the ICS661.  
Pin compatible to CY24204-3  
Please contact IDT if you have a requirement for an  
input and output frequency not included in this  
document. IDT can rapidly modify this product to meet  
special requirements.  
Block Diagram  
VDD  
VDDL  
AVDD  
27 MHz  
CLKIN  
CLK1  
PLL Clock  
Synthesis  
CLK2  
Output  
Multiplexer  
and Dividers  
REFOUT1  
REFOUT2  
FS1:0  
2
2
GNDA  
OE  
GND  
IDT™ / ICS™ DTV, STB CLOCK SOURCE  
1
ICS3771-18  
REV B 111307  

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