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IBM13Q16734HCB-10T PDF预览

IBM13Q16734HCB-10T

更新时间: 2024-10-28 23:57:39
品牌 Logo 应用领域
其他 - ETC 动态存储器
页数 文件大小 规格书
14页 262K
描述
x72 SDRAM Module

IBM13Q16734HCB-10T 数据手册

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IBM13Q16734HCB  
16M x 72 Registered SDRAM Module  
Features  
• 200-Pin JEDEC Standard, Registered 8-Byte  
Dual In-line Memory Module  
• Automatic and controlled Precharge Commands  
• Programmable Operation:  
• 16M x 72 Synchronous DRAM DIMM  
• Performance:  
-SDRAM CAS Latency: 2  
-Burst Type: Sequential or Interleave  
-Burst Length: 2  
-Operation: Burst Read and Write or Multiple  
Burst Read with Single Write  
CAS Latency = 2*  
Clock Frequency  
Clock Cycle  
-10  
66  
Units  
MHz  
ns  
f
t
t
CK  
15  
CK2  
AC2  
• Suspend Mode and Power Down Mode  
• 12/9/2 Addressing (Row/Column/Bank)  
• 4096 Refresh cycles distributed across 64ms  
• Parallel Presence Detect  
Clock Access Time  
11.3  
ns  
* SDRAM CAS latency = 2; DIMM CAS Latency = 3  
• Inputs and outputs are LVTTL (3.3V) compatible  
• Single 3.3V to 3.6V Power Supply  
• Single Pulsed RAS interface  
• Card size: 6.05" x 1.50" x 0.158"  
• Gold contacts  
• Fully Synchronous to positive Clock Edge  
• Data Mask control  
• SDRAMS in TSOP Type II Package  
• Auto Refresh (CBR) and Self Refresh  
Description  
IBM13Q16734HCB is a registered 200-pin Synchro-  
nous DRAM Dual In-line Memory Module (DIMM)  
which is organized as a 16Mx72 high-speed mem-  
ory array. The DIMM uses eighteen x8 SDRAMs in  
400mil TSOP II packages. The DIMM achieves high  
speed data transfer rates of up to 66MHz by  
employing a prefetch/pipeline hybrid architecture  
that supports the JEDEC 1N rule while allowing very  
low burst power.  
register and presented to the SDRAMs on the fol-  
lowing clock.  
Prior to any Access operation, the CAS latency,  
burst type, burst length, and burst operation type  
must be programmed into the DIMM by address  
inputs A0-A13 using the Mode Register Set cycle.  
The DIMM uses parallel presence detects imple-  
mented according to the JEDEC standard.  
The DIMM is intended to comply with all non-  
optional JEDEC standards set for the 200-pin regis-  
tered SDRAM DIMMs.  
All IBM 200-pin DIMMs provide a high performance,  
flexible 8-byte interface in a 6.05” long high-perfor-  
mance footprint. Related products include both EDO  
DRAM and SDRAM unbuffered DIMMs in both non-  
parity x64 and ECC-Optimized x72 configurations in  
the 168 pin form factor.  
All control and address signals are synchronized  
with the positive edge of an externally supplied  
clock. They are latched in an on-DIMM pipeline  
Card Outline  
(Front)  
(Back)  
1
101  
16 17  
116 117  
78 79  
178 179  
100  
200  
04K8915.C75644E  
6/00  
©IBM Corporation. All rights reserved.  
Use is further subject to the provisions at the end of this document.  
Page 1 of 14  

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