Datasheet > IBM13T8644HPC-10T

IBM13T8644HPC-10T

更新时间： 2024-10-28 23:57:39

品牌	Logo	应用领域
其他 - ETC		动态存储器
页数	文件大小	规格书
17页	302K
描述
x64 SDRAM Module

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Discontinued (8/99 - last order; 12/99 - last ship)

IBM11M4730C4M

x 72 E12/10, 5.0V, Au.

IBM13T8644HPB

IBM13T8644HPC

8M x 64 SDRAM SO DIMM

Features

• 144 Pin JEDEC Standard, 8 Byte Small Outline

Dual-In-line Memory Module

• Programmable Operation:

- CAS Latency: 2, 3

- Burst Type: Sequential or Interleave

- Burst Length: 1, 2, 4, 8, Full-Page (Full-

Page supports Sequential burst only)

- Operation: Burst Read and Write or Multiple

Burst Read with Single Write

• 8Mx64 Synchronous DRAM SO DIMM

• Low Power

• Performance:

-360

-10

Units

• Data Mask for Byte Read/Write control

• Auto Refresh (CBR) and Self Refresh

• Automatic and controlled Precharge Commands

• Suspend Mode and Power Down Mode

• 12/9/2 Addressing (Row/Column/Bank)

• 4096 refresh cycles distributed across 64ms

• Serial Presence Detect

CAS Latency

Clock Frequency

Clock Cycle

100

MHz

Clock Access Time

• Inputs and outputs are LVTTL (3.3V) compatible

• Single 3.3V ± 0.3V Power Supply

• Single Pulsed RAS interface

• Card size:

- 2.66" x 1.15" x 0.149" (IBM13T8644HPB)

• SDRAMs have 4 internal banks

• Fully Synchronous to positive Clock Edge

- 2.66" x 1.05" x 0.149" (IBM13T8644HPC)

• Gold contacts

• SDRAMS in TSOP Type II Package

Description

IBM13T8644HPB and IBM13T8644HPC are

144-pin Synchronous DRAM Small Outline Dual

In-line Memory Modules (SO DIMMs) organized as

8Mx64 high-speed memory arrays. These SO

DIMMs use eight 8Mx8 SDRAMs in 400mil TSOP II

packages. They achieve high speed data transfer

rates of up to 100MHz by employing a prefetch/pipe-

line hybrid architecture that supports the JEDEC 1N

rule while allowing very low burst power.

necessary timings for each operation. A 12 bit

address bus accepts address information in a

row/column multiplexing arrangement.

Prior to any access operation, the CAS latency,

burst type, burst length, and burst operation type

must be programmed into the SO DIMM by address

inputs A0-A9 during the Mode Register Set cycle.

The SO DIMM uses serial presence detects imple-

mented via a serial EEPROM using the two pin IIC

protocol. The first 128 bytes of serial PD data are

used by the DIMM manufacturer. The last 128 bytes

are available to the customer.

The SO DIMM is intended to comply with all JEDEC

standards set for 144 pin SDRAM SO DIMMs.

All control, address, and data input/output circuits

are synchronized with the positive edge of the exter-

nally supplied clock inputs. All inputs are sampled at

the positive edge of each externally supplied clock

(CK0, CK1). Internal operating modes are defined

by combinations of the RAS, CAS, WE, S0, DQMB,

and CKE0 signals. A command decoder initiates the

All IBM 144-pin SO DIMMs provide a high perfor-

mance, flexible 8-byte interface in a 2.66" long

space-saving footprint. Related products are in the

EDO DRAM SO DIMM family.

Card Outline

(Front)

(Back)

143

144

01L5951.E24562B

5/99

Use is further subject to the provisions at the end of this document.

Page 1 of 17

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