Datasheet > IBM13T16644NPA-10T

IBM13T16644NPA-10T

更新时间： 2024-10-28 23:57:39

品牌	Logo	应用领域
其他 - ETC		动态存储器
页数	文件大小	规格书
16页	263K
描述
x72 SDRAM Module

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IBM13T16644NPA

16M x 64 Two Bank SDRAM SO DIMM

Features

• 144-Pin JEDEC Standard, 8-Byte Small Outline

Dual-In-line Memory Module

• 16Mx64 Synchronous DRAM SO DIMM

• Low Power

• Data Mask for Byte Read/Write control

• Programmable Operation:

- CAS Latency: 2, 3

- Burst Type: Sequential or Interleave

- Burst Length: 1, 2, 4, 8, Full-Page (Full-

Page supports Sequential burst only)

- Operation: Burst Read and Write or Multiple

Burst Read with Single Write

• Performance:

-10

Units

CAS Latency

Clock Frequency

Clock Cycle

100

MHz

• Auto Refresh (CBR) and Self Refresh

• Automatic and controlled Precharge Commands

• Suspend Mode and Power Down Mode

• 12/9/2 Addressing (Row/Column/Bank)

• 4096 refresh cycles distributed across 64ms

• Serial Presence Detect

• Card size: 2.66" x 1.15" x 0.149"

• Gold contacts

• SDRAMS in TSOP Type II Package

Clock Access Time

• Inputs and outputs are LVTTL (3.3V) compatible

• Single 3.3V ± 0.3V Power Supply

• Single Pulsed RAS interface

• SDRAMs have 4 internal banks

• Module has 2 physical banks

• Fully Synchronous to positive Clock Edge

Description

IBM13T16644NPA is a 144-pin Synchronous DRAM

Small Outline Dual In-line Memory Module (SO

DIMM) which is organized as a 16Mx64 high-speed

memory array and is configured as two 8Mx64 phys-

ical banks. The SO DIMM uses eight 8Mx16

SDRAMs in 400mil TSOP II packages. The SO

DIMM achieves high speed data transfer rates of up

to 100MHz by employing a prefetch/pipeline hybrid

architecture that supports the JEDEC 1N rule while

allowing very low burst power.

RAS, CAS, WE, S0, S1, DQMB, and CKE0, CKE1

signals. A command decoder initiates the necessary

timings for each operation. A 12-bit address bus

accepts address information in a row/column multi-

plexing arrangement.

Prior to any access operation, the CAS latency,

burst type, burst length, and burst operation type

must be programmed into the SO DIMM by address

inputs A0-A9 during the Mode Register Set cycle.

The SO DIMM uses serial presence detects imple-

mented via a serial EEPROM using the two pin IIC

protocol. The first 128 bytes of serial PD data are

used by the DIMM manufacturer. The last 128 bytes

are available to the customer.

The SO DIMM is intended to comply with all JEDEC

standards set for 144-pin SDRAM SO DIMMs.

All control, address, and data input/output circuits

are synchronized with the positive edge of the exter-

nally supplied clock inputs.

All IBM 144-pin SO DIMMs provide a high perfor-

mance, flexible 8-byte interface in a 2.66" long

space-saving footprint.

All inputs are sampled at the positive edge of each

externally supplied clock (CK0, CK1). Internal oper-

ating modes are defined by combinations of the

Use is further subject to the provisions at the end of this document.

06K2331.H00961

11/99

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与IBM13T16644NPA-10T相关器件

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IBM13T2649JC-12T	ETC	获取价格	x64 SDRAM Module
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IBM13T4644MPB-10T	IBM	获取价格	Synchronous DRAM Module, 4MX64, 7ns, CMOS
IBM13T4644MPC-10T	ETC	获取价格	x64 SDRAM Module
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IBM13T4644MPE-10T	ETC	获取价格	x64 SDRAM Module
IBM13T4644MPE-360T	ETC	获取价格	x64 SDRAM Module

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