Datasheet > IBM13T4644MPE-360T

IBM13T4644MPE-360T

更新时间： 2024-10-28 23:57:39

品牌	Logo	应用领域
其他 - ETC		动态存储器
页数	文件大小	规格书
17页	250K
描述
x64 SDRAM Module

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Discontinued (4/1/00 last order; 7/31/00 - last ship)

IBM11M4730C4M

x 72 E12/10, 5.0V, Au.

IBM13T4644MPE

4M x 64 PC100 SDRAM SO DIMM

Features

• 144 Pin JEDEC Standard, 8 Byte Small Outline

Dual-In-line Memory Module

• Programmable Operation:

- CAS Latency: 2, 3

- Burst Type: Sequential or Interleave

- Burst Length: 1, 2, 4, 8, Full-Page (Full-

Page supports Sequential burst only)

- Operation: Burst Read and Write or Multiple

Burst Read with Single Write

• 4Mx64 Synchronous DRAM SO DIMM

• Performance: PC100

-360

Units

CAS Latency

Clock Frequency

Clock Cycle

100

MHz

• Auto Refresh (CBR) and Self Refresh

• Automatic and controlled Precharge Commands

• Suspend Mode and Power Down Mode

• 12/8/2 Addressing (Row/Column/Bank)

• 4096 refresh cycles distributed across 64ms

• Serial Presence Detect

Clock Access Time

• Inputs and outputs are LVTTL (3.3V) compatible

• 10 Ohm Resistors on DQs

• Single 3.3V ± 0.3V Power Supply

• Single Pulsed RAS interface

• Card size: 2.66" x 1.0" x 0.149"

• Gold contacts

• SDRAMs have four internal banks

• Fully Synchronous to positive Clock Edge

• Data Mask for Byte Read/Write control

• SDRAMS in TSOP Type II Package

Description

IBM13T4644MPE is a 144-pin Synchronous DRAM

Small Outline Dual In-line Memory Module (SO

DIMM) which is organized as a 4Mx64 high-speed

memory array. The SO DIMM uses four 4Mx16

SDRAMs in 400mil TSOP II packages and achieves

high speed data transfer rates of up to 100MHz by

employing a prefetch/pipeline hybrid architecture

that supports the JEDEC 1N rule while allowing very

low burst power. The SO DIMM is intended to com-

ply with all JEDEC and INTEL PC100 rev 1.2 stan-

dards set for 144 pin SDRAM SO DIMMs.

and CKE0 signals. A command decoder initiates the

necessary timings for each operation. A 12 bit

address bus accepts address information in a

row/column multiplexing arrangement.

Prior to any access operation, the CAS latency,

burst type, burst length, and burst operation type

must be programmed into the SO DIMM by address

inputs A0-A9 during the mode register set cycle.

The SO DIMM uses serial presence detects imple-

mented via a serial EEPROM using the two pin IIC

protocol. The first 128 bytes of serial PD data are

used by the DIMM manufacturer. The last 128 bytes

are available to the customer.

All control, address, and data input/output circuits

are synchronized with the positive edge of the exter-

nally supplied clock inputs. All inputs are sampled at

the positive edge of the externally supplied clock

(CK0). Internal operating modes are defined by

combinations of the RAS, CAS, WE, S0, DQMB,

All IBM 144-pin SO DIMMs provide a high perfor-

mance, flexible 8-byte interface in a 2.66" long

space-saving footprint.

Use is further subject to the provisions at the end of this document.

45L7084.E93888B

10/99

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与IBM13T4644MPE-360T相关器件

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