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IBM13T4644MPC-10T PDF预览

IBM13T4644MPC-10T

更新时间: 2024-10-28 23:57:39
品牌 Logo 应用领域
其他 - ETC 动态存储器
页数 文件大小 规格书
14页 258K
描述
x64 SDRAM Module

IBM13T4644MPC-10T 数据手册

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Discontinued (8/99 - last order; 12/99 - last ship)  
IBM13T4644MPC2M  
x 6411/8/1, 3.3V 14.  
IBM13T4644MPC  
4M x 64 SDRAM SO DIMM  
Features  
• 144 Pin (emerging) JEDEC Standard, 8 Byte  
Small Outline Dual-In-line Memory Module  
• Programmable Operation:  
- CAS Latency: 2, 3  
- Burst Type: Sequential or Interleave  
- Burst Length: 1, 2, 4, 8, Full-Page (Full-  
Page supports Sequential burst only)  
- Operation: Burst Read and Write or Multiple  
Burst Read with Single Write  
• 4Mx64 Synchronous DRAM SO DIMM  
• Performance:  
10  
3
Units  
CAS Latency  
f
t
t
Clock Frequency  
Clock Cycle  
100  
10  
7
MHz  
ns  
CK  
CK  
AC  
• Auto Refresh (CBR) and Self Refresh  
• Automatic and controlled Precharge Commands  
• Suspend Mode and Power Down Mode  
• 12/8/2 Addressing (Row/Column/Bank)  
• 4096 refresh cycles distributed across 64ms  
• Serial Presence Detect  
Clock Access Time  
ns  
• Inputs and outputs are LVTTL (3.3V) compatible  
• Single 3.3V ±0.3V Power Supply  
• Single Pulsed RAS interface  
• SDRAMs have four internal banks  
• Fully Synchronous to positive Clock Edge  
• Data Mask for Byte Read/Write control  
• Card size: 2.66" x 1.0" x 0.149"  
• Gold contacts  
• SDRAMS in TSOP Type II Package  
Description  
IBM13T4644MPC is a 144-pin Synchronous DRAM  
Small Outline Dual In-line Memory Module (SO  
DIMM) which is organized as a 4Mx64 high-speed  
memory array. The SO DIMM uses four 4Mx16  
SDRAMs in 400mil TSOP II packages and achieves  
high speed data transfer rates of up to 100MHz by  
employing a prefetch/pipeline hybrid architecture  
that supports the JEDEC 1N rule while allowing very  
low burst power. The SO DIMM is intended to com-  
ply with all JEDEC standards set for 144 pin  
SDRAM SO DIMMs.  
necessary timings for each operation. A 14 bit  
address bus accepts address information in a  
row/column multiplexing arrangement.  
Prior to any access operation, the CAS latency,  
burst type, burst length, and burst operation type  
must be programmed into the SO DIMM by address  
inputs A0-A9 during the mode register set cycle.  
The SO DIMM uses serial presence detects imple-  
mented via a serial EEPROM using the two pin IIC  
protocol. The first 128 bytes of serial PD data are  
used by the DIMM manufacturer. The last 128 bytes  
are available to the customer.  
All control, address, and data input/output circuits  
are synchronized with the positive edge of the exter-  
nally supplied clock inputs. All inputs are sampled at  
the positive edge of the externally supplied clock  
(CK0). Internal operating modes are defined by  
combinations of the RAS, CAS, WE, S0, DQMB,  
and CKE0 signals. A command decoder initiates the  
All IBM 144-pin SO DIMMs provide a high perfor-  
mance, flexible 8-byte interface in a 2.66" long  
space-saving footprint. Related products are in the  
EDO DRAM SO DIMM family.  
Card Outline  
(Front)  
(Back)  
1
2
59 61  
62  
143  
144  
60  
©IBM Corporation. All rights reserved.  
Use is further subject to the provisions at the end of this document.  
29L6293.E93850A  
3/99  

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