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IBM041812PQKB-8 PDF预览

IBM041812PQKB-8

更新时间: 2024-10-29 04:15:31
品牌 Logo 应用领域
国际商业机器公司 - IBM 静态存储器
页数 文件大小 规格书
14页 218K
描述
Standard SRAM, 64KX18, 8ns, CMOS, PQFP100, TQFP-100

IBM041812PQKB-8 数据手册

 浏览型号IBM041812PQKB-8的Datasheet PDF文件第1页浏览型号IBM041812PQKB-8的Datasheet PDF文件第2页浏览型号IBM041812PQKB-8的Datasheet PDF文件第3页浏览型号IBM041812PQKB-8的Datasheet PDF文件第5页浏览型号IBM041812PQKB-8的Datasheet PDF文件第6页浏览型号IBM041812PQKB-8的Datasheet PDF文件第7页 
IBM041812PQKB  
64K X 18 BURST SRAM  
Preliminary  
Burst SRAM Clock Truth Table  
CLK  
CS2  
H
CS2  
X
CS  
L
ADSP  
ADSC  
ADV  
X
WE  
X
OE  
X
DQ  
Operation  
LH  
LH  
LH  
LH  
L
L
X
X
L
L
High-Z Deselected Cycle  
High-Z Deselected Cycle  
High-Z Deselected Cycle  
High-Z Deselected Cycle  
X
L
L
X
X
X
H
X
X
X
X
X
X
X
X
L
X
X
X
X
Read from External  
Q
LH  
LH  
LH  
LH  
LH  
LH  
LH  
L
L
L
L
X
X
X
H
H
H
H
X
X
X
L
L
L
L
X
X
X
L
L
X
X
L
X
X
X
X
L
X
X
H
L
L
H
L
Address, Begin Burst  
Read from External  
High-Z  
Address, Begin Burst  
Read from External  
Q
H
H
H
H
H
Address, Begin Burst  
Write to External  
D
L
X
L
Address, Begin Burst  
Read from next Add.,  
Continue Burst  
H
H
H
H
L
Q
Write to next Add.,  
Continue Burst  
L
X
L
D
Read from Current  
Q
H
H
Add., Suspend Burst  
Write to Current Add.,  
LH  
LH  
LH  
X
X
X
X
X
X
X
H
H
H
X
X
H
L
H
X
L
L
X
H
X
X
L
D
Suspend Burst  
High-Z Deselect Cycle  
Read from next Add.,  
Continue Burst  
H
Q
Write to next Add.,  
LH  
LH  
LH  
X
X
X
X
X
X
H
H
H
X
X
X
H
H
H
L
H
H
L
H
L
X
L
D
Continue Burst  
Read from current  
Q
Add., Suspend Burst  
Write to current Add.,  
Suspend Burst  
X
D
1. For a write operation preceded by a read cycle, OE must be HIGH early enough to allow Input Data Setup, and must be kept HIGH  
through Input Data Hold Time.  
2. WE refers to WEa, WEb.  
3. ADSP is gated by CS, and CS is used to block ADSP when CS = VIH, as required in applications using Processor Address Pipelin-  
ing.  
4. All Addresses, Data In and Control signals are registered on the rising edge of CLK.  
Burst Sequence Truth Table  
(A1,A0)  
External Address  
A15-A2  
Notes  
(0,0)  
(0,0)  
(0,1)  
(1,0)  
(1,1)  
(0,1)  
(0,1)  
(0,0)  
(1,1)  
(1,0)  
(1,0)  
(1,0)  
(1,1)  
(0,0)  
(0,1)  
(1,1)  
(1,1)  
(1,0)  
(0,1)  
(0,0)  
1st Access  
2nd Access  
3rd Access  
4th Access  
A15-A2  
A15-A2  
A15-A2  
A15-A2  
©IBM Corporation. All rights reserved.  
Use is further subject to the provisions at the end of this document.  
26H4672  
SA14-4663-01  
Revised 9/97  
Page 4 of 14  

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