Datasheet > HYB25D512800AE-8

HYB25D512800AE-8

更新时间： 2024-11-19 08:18:11

品牌	Logo	应用领域
英飞凌 - INFINEON		动态存储器双倍数据速率光电二极管
页数	文件大小	规格书
75页	2025K
描述
DDR DRAM, 64MX8, 0.8ns, CMOS, PDSO66, 0.400 INCH, PLASTIC, TSOP2-66

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

HYB25D512800AE-8 数据手册

HYB25D512400/800/160AT(L)

512-MBit Double Data Rata SDRAM

Preliminary Datasheet V0.91, 2002-11-14

Features

• DLL aligns DQ and DQS transitions with CK

transitions

CAS Latency and Frequency

Maximum Operating Frequency (MHz)

• Commands entered on each positive CK edge;

data and data mask referenced to both edges of

DQS

CAS Latency

DDR200

-8

DDR266A

-7

DDR333

-6

100

125

133

143

133

166

2.5

• Burst Lengths: 2, 4, or 8

• CAS Latency: (1.5), 2, 2.5, 3

• Double data rate architecture: two data transfers

per clock cycle

• Auto Precharge option for each burst access

• Auto Refresh and Self Refresh Modes

• Bidirectional data strobe (DQS) is transmitted

and received with data, to be used in capturing

data at the receiver

• 7.8ꢀs Maximum Average Periodic Refresh

Interval

• DQS is edge-aligned with data for reads and is

center-aligned with data for writes

• 2.5V (SSTL_2 compatible) I/O

• V_DDQ= 2.5V Mꢁ0.2V

• V_DD= 2.5V Mꢁ0.2V

• Differential clock inputs (CK and CK)

• Four internal banks for concurrent operation

• Data mask (DM) for write data

• TSOP66 package

Description

The 512Mb DDR SDRAM is a high-speed CMOS,

dynamic random-access memory containing 536,870,912

bits. It is internally configured as a quad-bank DRAM.

dent with the Read or Write command are used to select

the bank and the starting column location for the burst

access.

The 512Mb DDR SDRAM uses a double-data-rate archi-

tecture to achieve high-speed operation. The double data

rate architecture is essentially a 2n prefetch architecture

with an interface designed to transfer two data words per

clock cycle at the I/O pins. A single read or write access

for the 512Mb DDR SDRAM effectively consists of a sin-

gle 2n-bit wide, one clock cycle data transfer at the inter-

nal DRAM core and two corresponding n-bit wide, one-

half-clock-cycle data transfers at the I/O pins.

The DDR SDRAM provides for programmable Read or

Write burst lengths of 2, 4 or 8 locations. An Auto Pre-

charge function may be enabled to provide a self-timed

row precharge that is initiated at the end of the burst

access.

As with standard SDRAMs, the pipelined, multibank archi-

tecture of DDR SDRAMs allows for concurrent operation,

thereby providing high effective bandwidth by hiding row

precharge and activation time.

A bidirectional data strobe (DQS) is transmitted externally,

along with data, for use in data capture at the receiver.

DQS is a strobe transmitted by the DDR SDRAM during

Reads and by the memory controller during Writes. DQS

is edge-aligned with data for Reads and center-aligned

with data for Writes.

An auto refresh mode is provided along with a power-sav-

ing power-down mode. All inputs are compatible with the

JEDEC Standard for SSTL_2. All outputs are SSTL_2,

Class II compatible.

Note: The functionality described and the timing specifi-

cations included in this data sheet are for the DLL Enabled

mode of operation.

The 512Mb DDR SDRAM operates from a differential

clock (CK and CK; the crossing of CK going HIGH and CK

going LOW is referred to as the positive edge of CK).

Commands (address and control signals) are registered at

every positive edge of CK. Input data is registered on both

edges of DQS, and output data is referenced to both

edges of DQS, as well as to both edges of CK.

Read and write accesses to the DDR SDRAM are burst

oriented; accesses start at a selected location and con-

tinue for a programmed number of locations in a pro-

grammed sequence. Accesses begin with the registration

of an Active command, which is then followed by a Read

or Write command. The address bits registered coincident

with the Active command are used to select the bank and

row to be accessed. The address bits registered coinci-

V0.91, 2002-11-14

Page 1 of 77

12 3 4 5 6 7...75

中文翻译

下载PDF

与HYB25D512800AE-8相关器件

型号	品牌	获取价格	描述	数据表
HYB25D512800AEL-6	INFINEON	获取价格	DDR DRAM, 64MX8, 0.7ns, CMOS, PDSO66, 0.400 INCH, PLASTIC, TSOP2-66
HYB25D512800AFL-6	INFINEON	获取价格	DDR DRAM, 64MX8, 0.7ns, CMOS, PBGA60, 18 X 10 MM, FBGA-60
HYB25D512800AT	INFINEON	获取价格	512Mbit Double Data Rate SDRAM
HYB25D512800AT-6	INFINEON	获取价格	512Mbit Double Data Rate SDRAM
HYB25D512800AT-7	INFINEON	获取价格	512Mbit Double Data Rate SDRAM
HYB25D512800AT-7F	INFINEON	获取价格	512Mbit Double Data Rate SDRAM
HYB25D512800AT-8	INFINEON	获取价格	DDR DRAM, 64MX8, 0.8ns, CMOS, PDSO66, 0.400 INCH, PLASTIC, TSOP2-66
HYB25D512800ATL-6	INFINEON	获取价格	DDR DRAM, 64MX8, 0.7ns, CMOS, PDSO66, 0.400 INCH, PLASTIC, TSOP2-66
HYB25D512800ATL-7	INFINEON	获取价格	DDR DRAM, 64MX8, 0.75ns, CMOS, PDSO66, 0.400 INCH, PLASTIC, TSOP2-66
HYB25D512800BC-5	INFINEON	获取价格	512Mbit Double Data Rate SDRAM

与HYB25D512800AE-8相关文章

解析光耦仿真器：升级光耦合器技术的必要性
2024-11-18

17
英伟达新一代Blackwell GPU过热问题致交付延迟
2024-11-18

12
国产厂商思特威CMOS图像传感器芯片单月出货超1亿颗，技术创新引领行业发展
2024-11-14

42
台积电5nm和3nm产能利用率达100%，半导体行业景气度持续攀升
2024-11-14

36

产品中心

服务支持

精选活动

关于我们

帮助中心

HYB25D512800AE-8

HYB25D512800AE-8 数据手册

与HYB25D512800AE-8相关器件

与HYB25D512800AE-8相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

HYB25D512800AE-8

HYB25D512800AE-8 数据手册

与HYB25D512800AE-8相关器件

与HYB25D512800AE-8相关文章

您还可以找

您在本页遇到什么问题？