Datasheet > HY5W26CF-H

HY5W26CF-H

更新时间： 2024-11-06 23:57:15

品牌	Logo	应用领域
其他 - ETC		动态存储器
页数	文件大小	规格书
24页	407K
描述
SDRAM\|4X2MX16\|CMOS\|BGA\|54PIN\|PLASTIC

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中文翻译

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HY5W26CF-H 数据手册

HY5W2A6C(L/S)F / HY57W2A1620HC(L/S)T

HY5W26CF / HY57W281620HCT

4Banks x 2M x 16bits Synchronous DRAM

DESCRIPTION

The Hynix Low Power SDRAM is suited for non-PC application which use the batteries such as PDAs,

2.5G and 3G cellular phones with internet access and multimedia capabilities, mini-notebook, handheld

PCs.

The Hynix HY5W2A6CF is a 134,217,728bit CMOS Synchronous Dynamic Random Access Memory. It

is organized as 4banks of 2,097,152x16.

The Low Power SDRAM provides for programmable options including CAS latency of 1, 2, or 3, READ

or WRITE burst length of 1, 2, 4, 8, or full page, and the burst count sequence(sequential or interleave).

And the Low Power SDRAM also provides for special programmable options including Partial Array Self

Refresh of a quarter bank, a half bank, 1bank, 2banks, or all banks, Temperature Compensated Self

Refresh of 15, 45, 70, or 85 degrees C. A burst of Read or Write cycles in progress can be terminated

by a burst terminate command or can be interrupted and replaced by a new burst Read or Write com-

mand on any cycle(This pipelined design is not restricted by a 2N rule).

Deep Power Down Mode is a additional operating mode for Low Power SDRAM. This mode can achieve

maximum power reduction by removing power to the memory array within each SDRAM. By using this

feature, the system can cut off alomost all DRAM power without adding the cost of a power switch and

giving up mother-board power-line layout flexibility.

FEATURES

•

Standard SDRAM Protocol

Internal 4bank operation

Voltage : VDD = 2.5V, VDDQ = 1.8V & 2.5V

LVTTL compatible I/O Interface

Low Voltage interface to reduce I/O power

Low Power Features ( HY5W26CF / HY57W281620HCT series can’t support these features)

- PASR(Partial Array Self Refresh)

- TCSR(Temperature Compensated Self Refresh)

- Deep Power Down Mode

•

CAS latency of 1, 2, or 3

Packages : 54ball, 0.8mm pitch FBGA / 54pin, TSOP

-25 ~ 85C Operation

128M SDRAM ODERING INFORMATION

Clock

CAS

Part Number

Organization

Interface

Package

Frequency Latency

HY5W2A6C(L/S)F-H

HY5W26CF-H

133MHz

100MHz

66Mhz

4banks x 2Mb x 16

LVTTL

HY57W2A1620HC(L/S)T-H

HY57W281620HCT-H

HY5W2A6C(L/S)F-P

HY5W26CF-P

HY57W2A1620HC(L/S)T-P

HY57W281620HCT-P

4banks x 2Mb x 16

LVTTL

54ball FBGA

(HY5xxxxxxF)

54pin TSOP-II

(HY5xxxxxxT)

HY5W2A6C(L/S)F-S

HY5W26CF-S

HY57W2A1620HC(L/S)T-S

HY57W281620HCT-S

HHY5W2A6C(L/S)F-B

HY5W26CF-B

HY57W2A1620HC(L/S)T-B

HY57W281620HCT-B

* HY5xxxxxx-B Series can support 40Mhz CL1 and 33Mhz CL1.

This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for

use of circuits described. No patent licenses are implied.

Rev. 1.3 / Dec. 01

12 3 4 5 6 7...24

中文翻译

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与HY5W26CF-H相关器件

型号	品牌	获取价格	描述	数据表
HY5W26CF-HF	HYNIX	获取价格	Synchronous DRAM, 8MX16, 5.4ns, CMOS, PBGA54, 8.30 X 10.50 MM, 0.80 MM PITCH, FBGA-54
HY5W26CF-P	HYNIX	获取价格	Synchronous DRAM, 8MX16, 7ns, CMOS, PBGA54, 8.30 X 10.50 MM, 0.80 MM PITCH, FBGA-54
HY5W26CF-PF	HYNIX	获取价格	Synchronous DRAM, 8MX16, 7ns, CMOS, PBGA54, 8.30 X 10.50 MM, 0.80 MM PITCH, FBGA-54
HY5W26CF-S	HYNIX	获取价格	Synchronous DRAM, 8MX16, 7ns, CMOS, PBGA54, 8.30 X 10.50 MM, 0.80 MM PITCH, FBGA-54
HY5W26CF-SF	HYNIX	获取价格	Synchronous DRAM, 8MX16, 7ns, CMOS, PBGA54, 8.30 X 10.50 MM, 0.80 MM PITCH, FBGA-54
HY5W26DF-H	HYNIX	获取价格	Synchronous DRAM, 8MX16, 5.4ns, CMOS, PBGA54, 0.80 MM PITCH, FBGA-54
HY5W26DLF-H	HYNIX	获取价格	Synchronous DRAM, 8MX16, 5.4ns, CMOS, PBGA54, 0.80 MM PITCH, FBGA-54
HY5W26DLFP-H	HYNIX	获取价格	Synchronous DRAM, 8MX16, 5.4ns, CMOS, PBGA54, 0.80 MM PITCH, LEAD FREE, FBGA-54
HY5W2A2(L/S)F	ETC	获取价格	4Mx32\|2.5V\|4K\|H\|Handy SDRAM - 128M
HY5W2A2(L/S)FC	ETC	获取价格	4Mx32\|2.5V\|4K\|H\|Handy SDRAM - 128M

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