Preliminary
HY5V72D(L/S)M(P) Series
4Banks x 4M x 32bits Synchronous DRAM
o
DC CHARACTERISTICS II (TA= 0 to 70 C)
Speed
Parameter
Symbol
Test Condition
Unit Note
H
P
Burst length=1, One bank active
tRC ≥ tRC(min), IOL=0mA
Operating Current
IDD1
240
220
mA
1
IDD2P
CKE ≤ VIL(max), tCK = 15ns
4
2
mA
mA
Precharge Standby Current
in Power Down Mode
IDD2PS CKE ≤ VIL(max), tCK = ∞
CKE ≥ VIH(min), CS ≥ VIH(min), tCK =
15ns
IDD2N
Input signals are changed one time during
2clks.
All other pins ≥ VDD-0.2V or ≤ 0.2V
30
Precharge Standby Current
in Non Power Down Mode
mA
mA
mA
CKE ≥ VIH(min), tCK = ∞
Input signals are stable.
IDD2NS
IDD3P
30
CKE ≤ VIL(max), tCK = 15ns
10
10
Active Standby Current
in Power Down Mode
IDD3PS CKE ≤ VIL(max), tCK = ∞
CKE ≥ VIH(min), CS ≥ VIH(min), tCK =
15ns
Input signals are changed one time during
2clks.
All other pins ≥ VDD-0.2V or ≤ 0.2V
IDD3N
60
40
Active Standby Current
in Non Power Down Mode
CKE ≥ VIH(min), tCK = ∞
Input signals are stable.
IDD3NS
CL=3
260
220
Burst Mode Operating Cur-
rent
tCK ≥ tCK(min), IOL=0mA
All banks active
IDD4
IDD5
mA
mA
mA
1
2
CL=2
280
440
240
400
Auto Refresh Current
Self Refresh Current
tRC ≥ tRC(min), All banks active
Nornal
6
3
IDD6
CKE ≤ 0.2V
Low Power
SL Power
1.8
mA
Note : 1. IDD1 and IDD4 depend on output loading and cycle rates. Specified values are measured with the output open
2. Min. of tRC (Refresh RAS cycle time) is shown at AC CHARACTERISTICS II
Rev. 0.2 / May. 2004
9