Datasheet > HY5V72DM-H

HY5V72DM-H

更新时间： 2024-01-16 07:51:42

品牌	Logo	应用领域
海力士 - HYNIX		动态存储器
页数	文件大小	规格书
13页	284K
描述
DRAM

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技术参数
数据手册

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HY5V72DM-H 技术参数

生命周期：	Obsolete	包装说明：	,
Reach Compliance Code：	unknown	风险等级：	5.84
Base Number Matches：	1

HY5V72DM-H 数据手册

Preliminary

HY5V72D(L/S)M(P) Series

4Banks x 4M x 32bits Synchronous DRAM

AC CHARACTERISTICS I (AC operating conditions unless otherwise noted)

Parameter

Symbol

tCK3

Unit

Note

Min

7.5

Max

Min

3.0

Max

System ClockCycle Time

CAS Latency=3

CAS Latency=2

1000

tCK2

tCHW

tCLW

tAC3

tAC2

tOH

Clock High Pulse Width

Clock Low Pulse Width

2.5

Access Time From Clock CAS Latency=3

CAS Latency=2

5.4

Data-out Hold Time

2.5

Data-Input Setup Time

Data-Input Hold Time

Address Setup Time

tDS

tDH

0.8

1.5

0.8

1.5

0.8

1.5

0.8

tAS

Address Hold Time

tAH

CKE Setup Time

tCKS

tCKH

tCS

CKE Hold Time

Command Setup Time

Command Hold Time

CLK to Data Output in Low-Z Time

tCH

tOLZ

tOHZ3

tOHZ2

CAS Latency=3

2.0

5.4

2.0

CLK to Data Output in

High-Z Time

CAS Latency=2

Note :

1. Assume tR / tF (input rise and fall time) is 1ns. If tR & tF > 1ns, then [(tR+tF)/2-1]ns should be added to the parameter.

2. Access time to be measured with input signals of 1V/ns edge rate, from 0.8V to 0.2V. If tR > 1ns,

then (tR/2-0.5)ns should be added to the parameter.

Rev. 0.2 / May. 2004

1...7 8 91011 12 13

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