Datasheet > HY57V28820ALT-10

HY57V28820ALT-10

更新时间： 2024-11-23 23:57:11

品牌	Logo	应用领域
其他 - ETC		动态存储器
页数	文件大小	规格书
13页	149K
描述
x8 SDRAM

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

HY57V28820ALT-10 数据手册

HY57V28820A

4Banks x 4M x 8bits Synchronous DRAM

DESCRIPTION

The Hyundai HY57V28820A is a 134,217,728bit CMOS Synchronous DRAM, ideally suited for the main memory appli-

cations which require large memory density and high bandwidth. HY57V28820A is organized as 4banks of

4,194,304x8.

HY57V28820A is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs

are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high

bandwidth. All input and output voltage levels are compatible with LVTTL.

Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write

cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count

sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate

command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined

design is not restricted by a `2N` rule.)

FEATURES

•

Single 3.3±0.3V power supply

•

Auto refresh and self refresh

All device pins are compatible with LVTTL interface

4096 refresh cycles / 64ms

JEDEC standard 400mil 54pin TSOP-II with 0.8mm

of pin pitch

Programmable Burst Length and Burst Type

- 1, 2, 4, 8 or Full Page for Sequential Burst

- 1, 2, 4 or 8 for Interleave Burst

•

All inputs and outputs referenced to positive edge of

system clock

•

Data mask function by DQM

Internal four banks operation

•

Programmable CAS Latency ; 2, 3 Clocks

ORDERING INFORMATION

Part No.

Clock Frequency

Power

Organization

Interface

Package

HY57V28820AT-6

HY57V28820AT-K

HY57V28820AT-H

HY57V28820AT-8

HY57V28820AT-P

HY57V28820AT-S

HY57V28820AT-10

HY57V28820ALT-6

HY57V28820ALT-K

HY57V28820ALT-H

HY57V28820ALT-8

HY57V28820ALT-P

HY57V28820ALT-S

HY57V28820ALT-10

166MHz

133MHz

125MHz

100MHz

166MHz

133MHz

125MHz

100MHz

Normal

4Banks x 4Mbits

x 8

LVTTL

400mil 54pin TSOP II

Low power

This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any

responsibility for use of circuits described. No patent licenses are implied.

Rev. 1.0/Dec.99

12 3 4 5 6 7...13

中文翻译

下载PDF

与HY57V28820ALT-10相关器件

型号	品牌	获取价格	描述	数据表
HY57V28820ALT-6	ETC	获取价格	x8 SDRAM
HY57V28820ALT-8	ETC	获取价格	x8 SDRAM
HY57V28820ALT-H	ETC	获取价格	x8 SDRAM
HY57V28820ALT-K	ETC	获取价格	x8 SDRAM
HY57V28820ALT-P	HYNIX	获取价格	Synchronous DRAM, 16MX8, 6ns, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, TSOP2-54
HY57V28820ALT-S	ETC	获取价格	x8 SDRAM
HY57V28820AT	ETC	获取价格	16Mx8\|3.3V\|4K\|6/K/H/8/P/S\|SDR SDRAM - 128M
HY57V28820AT-10	ETC	获取价格	x8 SDRAM
HY57V28820AT-6	ETC	获取价格	x8 SDRAM
HY57V28820AT-8	ETC	获取价格	x8 SDRAM