HY57V28820AT-SI

更新时间： 2024-11-27 12:58:39

品牌	Logo	应用领域
海力士 - HYNIX		存储内存集成电路光电二极管动态存储器时钟
页数	文件大小	规格书
11页	175K
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HY57V28820AT-SI 数据手册

HY57V28820HC(L)T-I

4Banks x 4M x 8bits Synchronous DRAM

DESCRIPTION

The Hynix HY57V28820HC(L)T is a 134,217,728bit CMOS Synchronous DRAM, ideally suited for the Mobile applica-

tions which require low power consumption and extended temperature range. f HY57V28820HC(L)T is organized as

4banks of 4,194,304x8.

HY57V28820HC(L)T is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and

outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very

high bandwidth. All input and output voltage levels are compatible with LVTTL.

Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write

cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count

sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate

command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined

design is not restricted by a `2N` rule.)

FEATURES

•

Single 3.3±0.3V power supply

•

Auto refresh and self refresh

All device pins are compatible with LVTTL interface

4096 refresh cycles / 64ms

JEDEC standard 400mil 54pin TSOP-II with 0.8mm

of pin pitch

Programmable Burst Length and Burst Type

- 1, 2, 4, 8 or Full Page for Sequential Burst

- 1, 2, 4 or 8 for Interleave Burst

•

All inputs and outputs referenced to positive edge of

system clock

•

Data mask function by DQM

Internal four banks operation

•

Programmable CAS Latency ; 2, 3 Clocks

ORDERING INFORMATION

Part No.

Clock Frequency

Power

Organization

Interface

Package

HY57V28820HCT-6I

HY57V28820HCT-KI

HY57V28820HCT-HI

HY57V28820HCT-8I

HY57V28820HCT-PI

HY57V28820HCT-SI

HY57V28820HCLT-6I

HY57V28820HCLT-KI

HY57V28820HCLT-HI

HY57V28820HCLT-8I

HY57V28820HCLT-PI

HY57V28820HCLT-SI

166MHz

133MHz

125MHz

100MHz

166MHz

133MHz

125MHz

100MHz

Normal

4Banks x 4Mbits

x 8

LVTTL

400mil 54pin TSOP II

Low power

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any

responsibility for use of circuits described. No patent licenses are implied.

Rev. 0.1/Jan. 02

12 3 4 5 6 7...11

中文翻译

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与HY57V28820AT-SI相关器件

型号	品牌	获取价格	描述	数据表
HY57V28820BLT	ETC	获取价格	16Mx8\|3.3V\|4K\|6/K/H/8/P/S\|SDR SDRAM - 128M
HY57V28820BLT-6	HYNIX	获取价格	Synchronous DRAM, 16MX8, 5.4ns, CMOS, PDSO54, 0.400 X 0.875 INCH, TSOP2-54
HY57V28820BLT-S	HYNIX	获取价格	Synchronous DRAM, 16MX8, 6ns, CMOS, PDSO54, 0.400 X 0.875 INCH, TSOP2-54
HY57V28820BT	ETC	获取价格	16Mx8\|3.3V\|4K\|6/K/H/8/P/S\|SDR SDRAM - 128M
HY57V28820BT-8	HYNIX	获取价格	Synchronous DRAM, 16MX8, 6ns, CMOS, PDSO54, 0.400 X 0.875 INCH, TSOP2-54
HY57V28820BT-H	HYNIX	获取价格	Synchronous DRAM, 16MX8, 5.4ns, CMOS, PDSO54, 0.400 X 0.875 INCH, TSOP2-54
HY57V28820BT-K	HYNIX	获取价格	Synchronous DRAM, 16MX8, 5.4ns, CMOS, PDSO54, 0.400 X 0.875 INCH, TSOP2-54
HY57V28820BT-P	HYNIX	获取价格	暂无描述
HY57V28820BT-S	HYNIX	获取价格	Synchronous DRAM, 16MX8, 6ns, CMOS, PDSO54, 0.400 X 0.875 INCH, TSOP2-54
HY57V28820ET-H	HYNIX	获取价格	Synchronous DRAM, 16MX8, 5.4ns, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, TSOP2-54

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