Datasheet > HY57V2578020TC-10P

HY57V2578020TC-10P

更新时间： 2024-09-10 09:18:23

品牌	Logo	应用领域
海力士 - HYNIX		动态存储器光电二极管
页数	文件大小	规格书
11页	126K
描述
Synchronous DRAM, 32MX8, 6ns, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, TSOP2-54

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HY57V2578020

4Banks x 8M x 8Bit Synchronous DRAM

Preliminary

DESCRIPTION

The Hyundai HY57V2578020 is a 268,435,456bit CMOS Synchronous DRAM, ideally suited for the main memory

applications which require large memory density and high bandwidth. HY57V2578020 is organized as 4banks of

8,388,608x8.

HY57V2578020 is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and out-

puts are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very

high bandwidth. All input and output voltage levels are compatible with LVTTL.

Programmable options include the length of pipeline (Read latency of 1,2, or 3), the number of consecutive read or

write cycles initiated by a single control command (Burst length of 1,2,4,8, or full page), and the burst count

sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate

command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined

design is not restricted by a `2N` rule.)

FEATURES

•

Single 3.3V ± 0.3V power supply

•

Auto refresh and self refresh

All device pins are compatible with LVTTL interface

8192 refresh cycles / 64ms

JEDEC standard 400mil 54pin TSOP-II with 0.8mm

of pin pitch

Programmable Burst Length and Burst Type

- 1, 2, 4, 8 and Full Page for Sequential Burst

- 1, 2, 4 and 8 for Interleave Burst

Programmable CAS Latency ; 2, 3 Clocks

•

All inputs and outputs referenced to positive edge of

system clock

•

Data mask function by DQM

Internal four banks operation

•

ORDERING INFORMATION

Part No.

Clock Frequency

Power

Organization

Interface

Package

HY57V2578020TC-8

125MHz

100MHz

125MHz

100MHz

HY57V2578020TC-10P

HY57V2578020TC-10S

HY57V2578020TC-10

HY57V2578020LTC-8

HY57V2578020LTC-10P

HY57V2578020LTC-10S

HY57V2578020LTC-10

Normal

4Banks x 8Mbits

LVTTL

400mil 54pin TSOP II

Low Power

This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any

responsibility for use of circuits described. No patent licenses are implied.

Revision 0.1 / Jul.98

12 3 4 5 6 7...11

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与HY57V2578020TC-10P相关器件

型号	品牌	获取价格	描述	数据表
HY57V2578020TC-10S	HYNIX	获取价格	Synchronous DRAM, 32MX8, 6ns, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, TSOP2-54
HY57V2578020TC-8	HYNIX	获取价格	Synchronous DRAM, 32MX8, 6ns, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, TSOP2-54
HY57V281620A	HYNIX	获取价格	4 Banks x 2M x 16bits Synchronous DRAM
HY57V281620ALT	ETC	获取价格	8Mx16\|3.3V\|4K\|6\|SDR SDRAM - 128M
HY57V281620ALT-10	ETC	获取价格	x16 SDRAM
HY57V281620ALT-6	HYNIX	获取价格	4 Banks x 2M x 16bits Synchronous DRAM
HY57V281620ALT-7	HYNIX	获取价格	4 Banks x 2M x 16bits Synchronous DRAM
HY57V281620ALT-8	HYNIX	获取价格	4 Banks x 2M x 16bits Synchronous DRAM
HY57V281620ALT-H	HYNIX	获取价格	4 Banks x 2M x 16bits Synchronous DRAM
HY57V281620ALT-HI	HYNIX	获取价格	4 Banks x 2M x 16bits Synchronous DRAM

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