HY57V2578020
4Banks x 8M x 8Bit Synchronous DRAM
Preliminary
DESCRIPTION
The Hyundai HY57V2578020 is a 268,435,456bit CMOS Synchronous DRAM, ideally suited for the main memory
applications which require large memory density and high bandwidth. HY57V2578020 is organized as 4banks of
8,388,608x8.
HY57V2578020 is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and out-
puts are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very
high bandwidth. All input and output voltage levels are compatible with LVTTL.
Programmable options include the length of pipeline (Read latency of 1,2, or 3), the number of consecutive read or
write cycles initiated by a single control command (Burst length of 1,2,4,8, or full page), and the burst count
sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate
command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined
design is not restricted by a `2N` rule.)
FEATURES
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Single 3.3V ± 0.3V power supply
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Auto refresh and self refresh
All device pins are compatible with LVTTL interface
8192 refresh cycles / 64ms
JEDEC standard 400mil 54pin TSOP-II with 0.8mm
of pin pitch
Programmable Burst Length and Burst Type
- 1, 2, 4, 8 and Full Page for Sequential Burst
- 1, 2, 4 and 8 for Interleave Burst
Programmable CAS Latency ; 2, 3 Clocks
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All inputs and outputs referenced to positive edge of
system clock
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Data mask function by DQM
Internal four banks operation
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ORDERING INFORMATION
Part No.
Clock Frequency
Power
Organization
Interface
Package
HY57V2578020TC-8
125MHz
100MHz
100MHz
100MHz
125MHz
100MHz
100MHz
100MHz
HY57V2578020TC-10P
HY57V2578020TC-10S
HY57V2578020TC-10
HY57V2578020LTC-8
HY57V2578020LTC-10P
HY57V2578020LTC-10S
HY57V2578020LTC-10
Normal
4Banks x 8Mbits
x8
LVTTL
400mil 54pin TSOP II
Low Power
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Revision 0.1 / Jul.98