HSP45116/883
TM
Data Sheet
May 1999
FN2813.3
Numerically Controlled
Oscillator/Modulator
Features
• This Circuit is Processed in Accordance to MIL-STD-883
and is Fully Conformant Under the Provisions of
Paragraph 1.2.1.
The Intersil HSP45116/883 combines a high performance
quadrature numerically controlled oscillator (NCO) and a high
speed 16-bit Complex Multiplier/Accumulator (CMAC) on a
single IC. This combination of functions allows a complex
vector to be multiplied by the internally generated (cos, sin)
vector for quadrature modulation and demodulation. As shown
in the Block Diagram, the HSP45116/883 is divided into three
main sections. The Phase/Frequency Control Section (PFCS)
and the Sine/Cosine Section together form a complex NCO.
The CMAC multiplies the output of the Sine/Cosine Section
with an external complex vector.
• NCO and CMAC on One Chip
• 15MHz and 25.6MHz Versions
• 32-Bit Frequency Control
• 16-Bit Phase Modulation
• 16-Bit CMAC
• 0.006Hz Tuning Resolution at 25.6MHz
• Spurious Frequency Components < -90dBc
• Fully Static CMOS
The inputs to the Phase/Frequency Control Section consist
of a microprocessor interface and individual control lines.
The phase resolution of the PFCS is 32 bits, which results in
frequency resolution better than 0.006Hz at 25.6MHz. The
output of the PFCS is the argument of the sine and cosine.
The spurious free dynamic range of the complex sinusoid is
greater than 90dBc.
Applications
• Frequency Synthesis
• Modulation - AM, FM, PSK, FSK, QAM
• Demodulation, PLL
The output vector from the Sine/Cosine Section is one of the
inputs to the Complex Multiplier/Accumulator. The CMAC mul-
tiplies this (cos, sin) vector by an external complex vector and
can accumulate the result. The resulting complex vectors are
available through two 20-bit output ports which maintain the
90dB spectral purity. This result can be accumulated internally
to implement an accumulate and dump filter.
• Phase Shifter
• Polar to Cartesian Conversions
Ordering Information
TEMP.
RANGE ( C)
PKG.
NO.
o
PART NUMBER
HSP45116GM-15/883
HS45116GM-25/883
PACKAGE
A quadrature down converter can be implemented by
loading a center frequency into the Phase/Frequency
Control Section. The signal to be downconverted is the
Vector Input of the CMAC, which multiplies the data by the
rotating vector from the Sine/Cosine Section. The resulting
complex output is the down converted signal.
-55 to 125 145 Ld PGA
-55 to 125 145 Ld PGA
G145.A
G145.A
Block Diagram
VECTOR INPUT
R
I
SINE/
COSINE
ARGUMENT
MICROPROCESSOR
PHASE/
SIN
INTERFACE
SINE/
COSINE
SECTION
FREQUENCY
CMAC
CONTROL
COS
INDIVIDUAL
SECTION
CONTROL SIGNALS
R
I
VECTOR OUTPUT
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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