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HSP43220GM-25/883 PDF预览

HSP43220GM-25/883

更新时间: 2024-02-01 01:04:39
品牌 Logo 应用领域
英特矽尔 - INTERSIL 外围集成电路LTE时钟
页数 文件大小 规格书
7页 194K
描述
Decimating Digital Filter

HSP43220GM-25/883 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:PGA, PGA84M,11X11Reach Compliance Code:unknown
ECCN代码:3A001.A.2.CHTS代码:8542.39.00.01
风险等级:5.66其他特性:ICC SPECIFIED @ 15MHZ
边界扫描:NO最大时钟频率:25.6 MHz
外部数据总线宽度:16JESD-30 代码:S-CPGA-P84
JESD-609代码:e0低功率模式:NO
端子数量:84最高工作温度:125 °C
最低工作温度:-55 °C输出数据总线宽度:24
封装主体材料:CERAMIC, METAL-SEALED COFIRED封装代码:PGA
封装等效代码:PGA84M,11X11封装形状:SQUARE
封装形式:GRID ARRAY电源:5 V
认证状态:Not Qualified筛选级别:38535Q/M;38534H;883B
子类别:DSP Peripherals最大压摆率:120 mA
最大供电电压:5.5 V最小供电电压:4.5 V
标称供电电压:5 V表面贴装:NO
技术:CMOS温度等级:MILITARY
端子面层:Tin/Lead (Sn/Pb)端子形式:PIN/PEG
端子节距:2.54 mm端子位置:PERPENDICULAR
uPs/uCs/外围集成电路类型:DSP PERIPHERAL, DIGITAL FILTERBase Number Matches:1

HSP43220GM-25/883 数据手册

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HSP43220/883  
TM  
Data Sheet  
March 1999  
FN2802.3  
Decimating Digital Filter  
Features  
The HSP43220/883 Decimating Digital Filter is a linear  
phase low pass decimation filter which is optimized for  
filtering narrow band signals in a broad spectrum of a signal  
processing applications. The HSP43220/883 offers a single  
chip solution to signal processing application which have  
historically required several boards of ICs. This reduction in  
component count results in faster development times, as  
well as reduction of hardware costs.  
• This Circuit is Processed in Accordance to MIL-STD-883  
and is Fully Conformant Under the Provisions of  
Paragraph 1.2.1.  
• Single Chip Narrow Band Filter with up to 96dB  
Attenuation  
• DC to 25.6MHz Clock Rate  
• 16-Bit 2’s Complement Input  
The HSP43220/883 is implemented as a two stage filter  
structure. As seen in the Block Diagram, the first stage is a  
High Order Decimation Filter (HDF) which utilizes an  
efficient decimation (sample rate reduction) technique to  
obtain decimation up to 1024 through a coarse low-pass  
filtering process. The HDF provides up to 96dB aliasing  
rejection in the signal pass band. The second stage consists  
of a Finite Impulse Response (FIR) decimation filter  
structured as a transversal FIR filter with up to 512  
symmetric taps which can implement filters with sharp  
transition regions. The FIR can perform further decimation  
by up to 16 if required, while preserving the 96dB aliasing  
attenuation obtained by the HDF. The combined total  
decimation capability is 16,384.  
• 20-Bit Coefficients in FIR  
• 24-Bit Extended Precision Output  
• Programmable Decimation up to a Maximum of 16,384  
• Standard 16-Bit Microprocessor Interface  
• Filter Design Software Available DECIMATE™  
Applications  
• Very Narrow Band Filters  
• Zoom Spectral Analysis  
• Channelized Receivers  
Ordering Information  
The HSP43220/883 accepts 16-bit parallel data in 2’s  
complement format at sampling rates up to 30MSPS. It  
provides a 16-bit microprocessor compatible interface to  
simplify the task of programming and three-state outputs to  
allow the connection of several ICs to a common bus. The  
HSP43220/883 also provides the capability to bypass either  
the HDF or the FIR for additional flexibility.  
TEMP.  
PKG.  
NO.  
o
PART NUMBER  
HSP43220GM-15/883  
HSP43220GM-25/883  
RANGE ( C)  
PACKAGE  
-55 to 125 84 Ld PGA  
-55 to 125 84 Ld PGA  
G84.A  
G84.A  
Block Diagram  
DECIMATION UP TO 1024  
DECIMATION UP TO 16  
INPUT CLOCK  
DATA INPUT  
24  
HIGH ORDER  
DECIMATION  
FILTER  
FIR  
DECIMATION  
FILTER  
16  
16  
DATA OUT  
DATA READY  
CONTROL AND COEFFICIENTS  
FIR CLOCK  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc.  
Copyright © Intersil Americas Inc. 2002. All Rights Reserved  
1
DECIMATE™ is a trademark of Intersil Corporation. IBM PC, XT, AT, PS/2™ are trademarks of IBM Corporation.  

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