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HSP43220JC-25 PDF预览

HSP43220JC-25

更新时间: 2024-02-07 19:01:14
品牌 Logo 应用领域
英特矽尔 - INTERSIL 外围集成电路LTE时钟
页数 文件大小 规格书
19页 193K
描述
Decimating Digital Filter

HSP43220JC-25 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Active零件包装代码:QFN
包装说明:,针数:84
Reach Compliance Code:unknown风险等级:5.66
其他特性:ICC SPECIFIED @ 15MHZ边界扫描:NO
最大时钟频率:25.64 MHz外部数据总线宽度:16
JESD-30 代码:S-PQCC-J84低功率模式:YES
湿度敏感等级:4端子数量:84
最高工作温度:70 °C最低工作温度:
输出数据总线宽度:24封装主体材料:PLASTIC/EPOXY
封装形状:SQUARE封装形式:CHIP CARRIER
峰值回流温度(摄氏度):225认证状态:COMMERCIAL
最大供电电压:5.25 V最小供电电压:4.75 V
标称供电电压:5 V表面贴装:YES
技术:MOS温度等级:COMMERCIAL
端子面层:NOT SPECIFIED端子形式:J BEND
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
uPs/uCs/外围集成电路类型:DSP PERIPHERAL, DIGITAL FILTERBase Number Matches:1

HSP43220JC-25 数据手册

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HSP43220  
Data Sheet  
February 1999  
File Number 2486.7  
Decimating Digital Filter  
Features  
The HSP43220 Decimating Digital Filter is a linear phase  
low pass decimation filter which is optimized for filtering  
narrow band signals in a broad spectrum of a signal  
processing applications. The HSP43220 offers a single chip  
solution to signal processing applications which have  
historically required several boards of ICs. This reduction in  
component count results in faster development times as well  
as reduction of hardware costs.  
• Single Chip Narrow Band Filter with up to 96dB  
Attenuation  
• DC to 33MHz Clock Rate  
• 16-Bit 2’s Complement Input  
• 20-Bit Coefficients in FIR  
• 24-Bit Extended Precision Output  
• Programmable Decimation up to a Maximum of 16,384  
• Standard 16-Bit Microprocessor Interface  
• Filter Design Software Available DECIMATE™  
• Up to 512 Taps  
The HSP43220 is implemented as a two stage filter  
structure. As seen in the block diagram, the first stage is a  
high order decimation filter (HDF) which utilizes an efficient  
sample rate reduction technique to obtain decimation up to  
1024 through a coarse low-pass filtering process. The HDF  
provides up to 96dB aliasing rejection in the signal pass  
band. The second stage consists of a finite impulse  
response (FIR) decimation filter structured as a transversal  
FIR filter with up to 512 symmetric taps which can implement  
filters with sharp transition regions. The FIR can perform  
further decimation by up to 16 if required while preserving  
the 96dB aliasing attenuation obtained by the HDF. The  
combined total decimation capability is 16,384.  
Applications  
• Very Narrow Band Filters  
• Zoom Spectral Analysis  
• Channelized Receivers  
• Large Sample Rate Converter  
The HSP43220 accepts 16-bit parallel data in 2’s  
complement format at sampling rates up to 33 MSPS. It  
provides a 16-bit microprocessor compatible interface to  
simplify the task of programming and three-state outputs to  
allow the connection of several ICs to a common bus. The  
HSP43220 also provides the capability to bypass either the  
HDF or the FIR for additional flexibility.  
Ordering Information  
TEMP.  
o
PART NUMBER RANGE ( C)  
PACKAGE  
PKG. NO.  
HSP43220VC-33  
HSP43220JC-15  
HSP43220JC-25  
HSP43220JC-33  
HSP43220GC-25  
HSP43220GC-33  
0 to 70  
0 to 70  
0 to 0  
100 Ld MQFP Q100.14x20  
84 Ld PLCC  
84 Ld PLCC  
84 Ld PLCC  
84 Ld CPGA  
84 Ld CPGA  
N84.1.15  
N84.1.15  
N84.1.15  
G84.A  
0 to 70  
0 to 70  
0 to 70  
G84.A  
DECIMATE Software Development Tool (This software tool may be  
downloaded from our Internet site: http://www.intersil.com)  
Block Diagram  
DECIMATION UP TO 1024  
DECIMATION UP TO 16  
INPUT CLOCK  
24  
HIGH ORDER  
DECIMATION  
FILTER  
FIR  
DECIMATION  
FILTER  
16  
16  
DATA OUT  
DATA INPUT  
DATA READY  
CONTROL AND COEFFICIENTS  
FIR CLOCK  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999  
DECIMATE™ is a trademark of Intersil Corporation.  
3-194  

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