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HD74LS645FPEL-E PDF预览

HD74LS645FPEL-E

更新时间: 2024-11-06 13:08:19
品牌 Logo 应用领域
瑞萨 - RENESAS 总线收发器
页数 文件大小 规格书
7页 79K
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HD74LS645FPEL-E 数据手册

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HD74LS645  
Octal Bus Transceivers (non-inverted 3-state outputs)  
REJ03D0491–0200  
Rev.2.00  
Feb.18.2005  
This octal bus transceivers is designed for asynchronous two-way communication between data buses. The devices  
transmit data from the A bus to the B bus or from the B bus to the A bus depending upon the level at the direction  
control (DIR) input. The enable input (G) can be used to disable the device so that the buses are effectively isolated.  
Features  
Ordering Information  
Package Code  
(Previous Code)  
Package  
Abbreviation  
Taping Abbreviation  
(Quantity)  
Part Name  
Package Type  
DILP-20 pin  
PRDP0020AC-B  
(DP-20NEV)  
HD74LS645P  
HD74LS645FPEL  
P
PRSP0020DD-B  
(FP-20DAV)  
SOP-20 pin (JEITA)  
FP  
EL (2,000 pcs/reel)  
Note: Please consult the sales office for the above package availability.  
Pin Arrangement  
1
2
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
DIR  
1A  
VCC  
Enable G  
1B  
3
2A  
4
3A  
2B  
5
4A  
3B  
6
5A  
4B  
7
6A  
5B  
8
7A  
6B  
9
8A  
7B  
10  
GND  
8B  
(Top view)  
Function Table  
Enable  
Direction Control  
Operation  
G
L
DIR  
L
B data to A bus  
A data to B bus  
Isolation  
L
H
H
X
Note: H; high level, L; low level, X; irrelevant  
Rev.2.00, Feb.18.2005, page 1 of 6  

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