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HD74LS645P PDF预览

HD74LS645P

更新时间: 2024-11-06 05:35:15
品牌 Logo 应用领域
瑞萨 - RENESAS 总线驱动器总线收发器逻辑集成电路光电二极管
页数 文件大小 规格书
7页 79K
描述
Octal Bus Transceivers (non-inverted 3-state outputs)

HD74LS645P 技术参数

是否Rohs认证:符合生命周期:Obsolete
零件包装代码:DIP包装说明:6.30 X 24.50 MM, 2.54 PITCH, PLASTIC, DIP-20
针数:20Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.23
Is Samacsys:N控制类型:COMMON CONTROL
计数方向:BIDIRECTIONAL系列:LS
JESD-30 代码:R-PDIP-T20长度:24.5 mm
逻辑集成电路类型:BUS TRANSCEIVER最大I(ol):0.024 A
湿度敏感等级:1位数:8
功能数量:1端口数量:2
端子数量:20最高工作温度:75 °C
最低工作温度:-20 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:DIP封装等效代码:DIP20,.3
封装形状:RECTANGULAR封装形式:IN-LINE
峰值回流温度(摄氏度):NOT SPECIFIED电源:5 V
Prop。Delay @ Nom-Sup:15 ns传播延迟(tpd):15 ns
认证状态:Not Qualified座面最大高度:5.08 mm
子类别:Bus Driver/Transceivers最大供电电压 (Vsup):5.25 V
最小供电电压 (Vsup):4.75 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:TTL
温度等级:COMMERCIAL EXTENDED端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED翻译:N/A
宽度:7.62 mmBase Number Matches:1

HD74LS645P 数据手册

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HD74LS645  
Octal Bus Transceivers (non-inverted 3-state outputs)  
REJ03D0491–0200  
Rev.2.00  
Feb.18.2005  
This octal bus transceivers is designed for asynchronous two-way communication between data buses. The devices  
transmit data from the A bus to the B bus or from the B bus to the A bus depending upon the level at the direction  
control (DIR) input. The enable input (G) can be used to disable the device so that the buses are effectively isolated.  
Features  
Ordering Information  
Package Code  
(Previous Code)  
Package  
Abbreviation  
Taping Abbreviation  
(Quantity)  
Part Name  
Package Type  
DILP-20 pin  
PRDP0020AC-B  
(DP-20NEV)  
HD74LS645P  
HD74LS645FPEL  
P
PRSP0020DD-B  
(FP-20DAV)  
SOP-20 pin (JEITA)  
FP  
EL (2,000 pcs/reel)  
Note: Please consult the sales office for the above package availability.  
Pin Arrangement  
1
2
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
DIR  
1A  
VCC  
Enable G  
1B  
3
2A  
4
3A  
2B  
5
4A  
3B  
6
5A  
4B  
7
6A  
5B  
8
7A  
6B  
9
8A  
7B  
10  
GND  
8B  
(Top view)  
Function Table  
Enable  
Direction Control  
Operation  
G
L
DIR  
L
B data to A bus  
A data to B bus  
Isolation  
L
H
H
X
Note: H; high level, L; low level, X; irrelevant  
Rev.2.00, Feb.18.2005, page 1 of 6  

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