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HD74HCT137P PDF预览

HD74HCT137P

更新时间: 2024-11-05 20:28:11
品牌 Logo 应用领域
瑞萨 - RENESAS 驱动光电二极管输出元件逻辑集成电路
页数 文件大小 规格书
7页 51K
描述
HCT SERIES, OTHER DECODER/DRIVER, INVERTED OUTPUT, PDIP16, DP-16

HD74HCT137P 技术参数

是否无铅:含铅是否Rohs认证:不符合
生命周期:Contact Manufacturer零件包装代码:DIP
包装说明:DP-16针数:16
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.41
Is Samacsys:N系列:HCT
输入调节:STANDARDJESD-30 代码:R-PDIP-T16
JESD-609代码:e0长度:19.2 mm
逻辑集成电路类型:OTHER DECODER/DRIVER功能数量:1
端子数量:16最高工作温度:85 °C
最低工作温度:-40 °C输出极性:INVERTED
封装主体材料:PLASTIC/EPOXY封装代码:DIP
封装形状:RECTANGULAR封装形式:IN-LINE
峰值回流温度(摄氏度):NOT SPECIFIED传播延迟(tpd):60 ns
认证状态:Not Qualified座面最大高度:5.06 mm
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:NO
技术:CMOS温度等级:INDUSTRIAL
端子面层:TIN LEAD端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:7.62 mm
Base Number Matches:1

HD74HCT137P 数据手册

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HD74HCT137  
3-to-8-line Decoder/Demultiplexer with Address Latch  
ADE-205-546 (Z)  
1st. Edition  
Sep. 2000  
Description  
The HD74HCT137 implements a three-to-eight line decoder with latches on the three address inputs.  
When GL goes from low to high, the address present at the select inputs (A, B and C) is stored in the  
latches. As long as GL remains high no address changes will be recognized. Output enable controls, G1  
and G2, control the state of the outputs independently of the select or latch-enable inputs.  
All of the outputs are high unless G1 is high and G2 is low. The HD74HCT137 is ideally suited for the  
implementation of glitchfree decoders in stored-address applications in bus oriented systems.  
Features  
LSTTL Output Logic Level Compatibility as well as CMOS Output Compatibility  
High Speed Operation: tpd (A, B, C to Y) = 18 ns typ (CL = 50 pF)  
High Output Current: Fanout of 10 LSTTL Loads  
Wide Operating Voltage: VCC = 4.5 to 5.5 V  
Low Input Current: 1 µA max  
Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C)  

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